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Composable C Series API

Overview

The I/O  Node is the traditional FPGA API for reading and writing data from C  Series modules. For ease of use, the I/O Node abstracts away low-level  data formatting, module communications, and module timing details. The  I/O Node works well for most programmers, but in some cases you may want  to make changes to application behavior at runtime. For example, you  may want to change module settings, view or change details of module  timing and synchronization, or switch module types in a chassis slot  without downloading a new bitfile. The Composable C Series API provides a  much lower-level interface with C Series modules that enables you to  create a more flexible FPGA bitfile.

In  the current version of the Composable C Series API, National  Instruments has focused on providing the ability to switch module types  in a dynamic module slot. You can mix and match dynamic module slots with slots using other APIs such as the I/O Node and the Scan Engine.

See the installed and attached Introduction to the Composable C Series API.pdf file for more information.

(TW) I just added another example project to the downloads (Dynamic Project w SCTL.zip).  This was written using a cRIO 9074 chassis and the first 3 slots will support any of the modules.  More comments about this example are included in the comments below.

Requirements

Supported systems include:

  • LabVIEW 2011
  • LabVIEW Real-Time 2011
  • LabVIEW FPGA 2011
  • NI-RIO 4.0
  • CompactRIO Module Support 4.0.1
  • C Series Modules - NI 9201, NI 9215, NI 9234, NI 9263, and NI 9476 are supported. Other modules will be added upon request.
Comments
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I added another example to the download, "Dynamic Project w SCTL.zip".  This project (written using a 9074) will support any of the 5 documented modules in the first 3 slots.  To run the example you will need to install the Composable API, unzip the project, target your chassis/controller (and recompile if necessary) copy the configuration file to the RT controller. You will need to run the FPGA Top Level VI and the RT State Machine (Top Level) VI.  Notes on known bugs, potential future improvements, and more details on the VI are documented on the front panel. 

You can also check out a video of this example running here:

http://www.youtube.com/watch?v=KZ6jCvxSoE0

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Requested/Future Improvements (Please feel free to add and edit):

Allow synch of delta sigma modules

Documentation for more modules

Support for parallel digital modules

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Potential bugs and suggested code changes (Please feel free to add and edit):

Reading the cal constants doesn't seem to work

The 9201 documentation on "output from module data interpretation" seems wrong.  I think you need to invert the MSB.

Can't read any channels on 9201 other than ch 0.

Remove the "set module present" attribute.

Remove the "set stop engine" attribute.

Set engine so attributes are reset to default values.

Supply an "abort" function to allow graceful exit of the engine in case of a hang.

Check handshaking on engine states, sometime a hang will occur if sending commands too quickly.

Potentially check for # bytes in buffer before triggering a SPI comm.

Potentially don't buffer SPI data until trigger (to prevent data loss on transition to idle).

Provide a set of constants per slot for module IO (to reduce edit time/mistakes). 

Set the engine to run in a SCTL on the top level diagram to allow other data transfer mechanisms.

Encapsulate the FPGA scoped FIFOs in the engine subVI. 

Expose command pump API for configuration of the rest of the app (or use a standard FPGA mechanism) so all commands use the same mechanism. 

Make module documentation consistent. 

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Great Job! Let's take a look if it helps

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