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Welcome to the Virtex 5 DSP48E Multiply/Accumulate (MAC) IP block

The LabVIEW FPGA DSP48E block provides low level access to DSP48E slices available on Virtex 5 devices. This thread is intended to foster discussion about the project. Please post your questions, suggestions and applications here. Our team including R&D, marketing, and support will actively monitor this discussion.

Thanks,

Newton Petersen, Senior Engineer, LabVIEW FPGA R&D

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Message 1 of 12
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is there a driver available for the Xilinx XUP V5 board (XUPV5-LX110T)? If that is available I can play with it.

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Message 2 of 12
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Does the MAC IP block currently exist or are we just talking about what features we'd like?

If it does exist where can I download it?

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Message 3 of 12
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That... was fast. Posting the download page for an actual block to play with is in progress. I believe this link should work now (if not, try back soon): http://decibel.ni.com/content/docs/DOC-7081

Thanks

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Message 4 of 12
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I do not believe there is target support available for the Xilinx XUP V5 board. Thank you for letting NI know this particular platform is of interest. NI is willing to create custom target support for boards like this under the right business circumstances so please consult with your local sales engineer concerning the possibilities.

You can run the DSP48E node in simulation under the "My Computer" target even if you do not have target support. Each call to the node simulates one clock cycle.

You can also compile for FPGA under one of the following Virtex 5 targets. You do not have to have the physical hardware to compile. You only need the RIO driver and target files along with LabVIEW FPGA 2009. This exercise will let you know what clock rate you can achieve with your logic you tested in simulation above.

IF RIO:
PXIe-5641R

FlexRIO:
PXI-7951R
PXI-7952R
PXI-7953R
PXI-7954R

R-Series:
PCIe-7841R
PCIe-7842R
PCIe-7851R
PCIe-7852R
PXI-7841r
PXI-7842r
PXI-7851r
PXI-7852r
PXI-7853r
PXI-7854r

Compact RIO:

cRIO-9111
cRIO-9112
cRIO-9113
cRIO-9114
cRIO-9116
cRIO-9118

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Message 5 of 12
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Maybe I'm missing something?

I thought the multiplication on the DSP48e was 25x18.  This seems to use a 30x18 multiplier.  Are you using extra logic slices to do this? Or are you using 2 DSPs to do a wider bit multiply before the Accumulator on the second DSP?

I would have assumed the IP block would have the ability to configure the width of the numbers going in / out (e.g. 4bits x 15bits + 17bits = 42bits).

I was also hoping that this project was a wrapper for the entire DSP48E block and not just the narrow use case of a Multiply w/ Accumulate.  I guess I'll just stick with core gen for now.

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Message 6 of 12
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Oh wait...I see.  If I double click on it I can configure it.  Why isn't this on the right-click menu?

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Message 7 of 12
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The multiplier is only 25x18 bits, so the upper 5 bits of the "a" input are unused when doing a multiplication. If you configure the node to perform p = a:b + c, a:b uses full 30 bits of a. This option shows when you choose Direct for a input. This is documented however it would certainly be clearer if we changed the input type based on the dialog selections.

This project is supposed to be a wrapper for all the raw, gory functionality available in the DSP48. As such, this block is not meant to be particularly easy to use. Let us know if there is something you know can be done with the DSP48 but cannot be done with this wrapper block...

Thanks

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Message 8 of 12
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That would be a bug. Good catch!

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Message 9 of 12
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Anyway we can get this for Labview 8.6?  I currently do not have 2009 installed with systems in the field.

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Message 10 of 12
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