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修改时间 04-03-2019 07:18 AM
大家好,我想导入一个CLIP进Labview FPGA的项目中。CLIP由一组.vhd文件(VHDL代码)组成,其中一些文件相互依赖关联。如果直接导入一个文件,Labview会报错说另一个相关的文件还没有编译进库里。但是即使我先导入报错提到的那个文件,还是解决不了问题。 请问大家有导入这种相互依赖的.vhd文件的经验吗?谢谢各位大大
如果问题中有遗漏或没描述清楚的地方,欢迎询问。
下图为Labview中导入CLIP时选择.vhd文件的界面:
修改时间 04-04-2019 01:00 AM
您好,
请问报错码是什么?可以截图吗?
修改时间 04-04-2019 04:01 AM
你好,这是报错的截图: 其中adcframe_lib, common为文件夹名, 文件已经上传. 我要编译的文件就在文件夹adcframe_lib/Vhdl里.
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