Why is LV FPGA DRAM Clock Rate so fast for new FlexRIO product? It was 166.7MHz for the previous FlexRIO 797xR series.
Since the new series require for users to access DRAM in such a fast clock domain, it maybe difficult to meet timing with some complex write/read addressing. Is there any plan to support lower clock speed with a wider DRAM data width?
In my past project, two 7976Rs are used to utilize two banks of DRAM to do some image processing.
New FlexRIO products are armed with two banks; therefore, I thought the same image processing can be accomplished with only one PXIe board. However, since new FlexRIO supports only a very fast clock rate to access DRAM, it looks not so straight forward.
LabVIEW FPGA and Software Designed Instrument Expert