Pin assignment

[vishal8583]

Hi,
      I am working on development of adapter module for FlexRio Card(PXI-7951R) using MDK.I need clarification regarding the pin
assignment. How do i assign a particular DataIn of type boolean to a particular pin on FPGA say GPIO_48(G20).The example in MDK is of vector type, doesnt indicate which user defined I/O is connected to
which pin in the FPGA bank.I would like to know how to connect a particular datatype to my choice of FPGA pins.

Vishal

[hagedornj]

Hello,

one possibility is to use a socketed Clip. In my design I have implemented a simple connection macro which makes the connection to the outside world:

(refer to the attached files)

SCIF0, SIF0, SCOF0, SOF0, SCKF0,_meas, SIF0_meas, SOF0_meas and SCKF0_DIR are internal signals which should be connected to the outside world.

You need the vhdl file and the xml file to get the pins available in the Project environment.

These file has to be stored at: C:\Documents and Settings\All Users\Documents\National Instruments\FlexRIO\IO Modules

To make the Pins available you have to go to the Properties of the IO-Modules (right mousebutton -> Properties on the IO-Modules)

-> Enable IO-Module

In case you have no Error you will find the IO ports in the Project Navigator Window.

In case you got xml errors (wrong xml coding) please use the Programmer's Notepad (freeware) (find via google). With this editor you can easily select the encoding:

     UTF-8 No Mark

Concerning different types

You can use boolean (single signals)

vhdl entry:

    P3_0_dir       : in std_logic;
xml sample:

     <Signal Name="P3_0_dir">
     <HDLName>P3_0_dir</HDLName>
     <Datatype><Boolean/></Datatype>
     <Direction>ToCLIP</Direction>
     <SignalType>data</SignalType>
    </Signal>
or 8 bit busses:
vhdl entry:

    P28_dir       : in std_logic_vector (7 downto 0);
xml sample

    <Signal Name="P28_dir">
     <HDLName>P28_dir</HDLName>
     <Datatype><U8/></Datatype>
     <Direction>ToCLIP</Direction>
     <SignalType>data</SignalType>
    </Signal>
or 16 bit busses:

vhdl entry:

    P29_dir       : in std_logic_vector (15 downto 0);
xml sample

    <Signal Name="P29_dir">
     <HDLName>P29_dir</HDLName>
     <Datatype><U16/></Datatype>
     <Direction>ToCLIP</Direction>
     <SignalType>data</SignalType>
    </Signal>
or 32 bi busses in same way

Bus types with other widthes are in my opinion not possible.

(please check the documentation)

Kind regards

Joerg

[vishal8583]

Hi,

        Thanx, been through your files, in your vhd file you have indicated " SCIF0  <= aUserGpio_n(27) " i want to knw which is the physical pin which it corresponds to on the FPGA (either it is in Bank0,Bank1 etc). All the pins are brought out to a connector on FlexRio Card. So i want to knw which pin it corresponds to.

Regards,