I want to synchronize a digital output and an analog input. So far, I know how to implement flat sequence - and I can synchronize my digital output sequences. What I am trying to do is, during one of those digital output (let's define that as signal C), I want to read from an analog signal. And that read needs to happen while C is on.
With my current setup, I think the analog read would start at the time I want, but I want it to finish when I want as well. And I would need to read the data within 1 micro second too.
Another issue is how do I continuously run this loops and keep reading the data and saving it to the FPGA? I know that with FIFO, it saves them in FPGA, but I may need millions of data. In that case, I need to transfer the data to the computer when the FPGA memory is nearly full. How do I do that?
Thanks in advance!
What hardware are you using? Have you taken a look at the getting started examples for that hardware?
You may also want to take a look at the High-Performance FPGA Developer's Guide. It provides a good introduction about what is different when writing FPGA code for a high throughput device that operates inside of a Single Cycle Timed Loop.
Thank you David for your reply.
I am using USB-7855R. I tied the getting started example, but it only has a vi where it actually have example for analog input. I can also make sync digital outputs as well as reading analog output. But I need to sync the analog reading with the digital outputs.
Most of the advice that people have received on the FlexRIO Network community group has been for FlexRIO devices. FPGA code for an sbRIO target will be very different from FPGA code written for a FlexRIO device. You may have better luck posting on the community forums than this community group. The LabVIEW board and the LabVIEW Embedded board are the ones you may consider posting on.
You may also want to open a service request if you would prefer to talk directly to an engineer at NI.
Also, you may want to take a step back and invest in some training. Everything you requested help for isn't too complicated by itself, but putting all that together is a lot of work and may be a little much to expect a complete response on the forum. If you don't have time to take training, a good alternative starting place would be chapter 5 of the cRIO developers guide.
I agree with David-A.
I have seen some very good hardware fail very badly due to the engineers mis-understanding of what is going on at the very low level.
LabVIEW and NI hardware does a very good job of abstracting the low level stuff for the sake of effeciency during designing.
At the same time regarding the Real Time and FPGA stuff LabVIEW has some very precise definitions of timing and how the LabVIEW primitives compile to the FPGA Fabric.
I have managed several FlexRIO projects with custom modules.
I am still amazed at the ModelSim simulation accuracy when compared to the actual hardware. My group has proven that we can do circles around the traditional VHDL design groups.