Compilation error for a complex multiplication.

[hjkee]

I am trying to compile a subVI having HDL interface node.

I've wrapped up a VHDL code, generated by xilinx logiCore, with a HDL interface in LV.

A function in VHDL has a complex multiplication, and a data sheet said that it would be synthesized with

DSP48e in Virtex-5 target. When I compile it, i got an error as follows:

>Status: Compilation failed due to a Compile Server error.

>

> Regenerating IP...
> ERROR:sim - Complex Multiplication : false is invalid.Finished Regenerating.
> ERROR:sim:57 - Error found during generation

Data sheet said that it  'Complex Multiplication' is always selected in virtex-5 target.

I guess that  ' Complex Multiplication' became 'false' during the compilation by some reason.

Do you have any idea to compile this successfully?

[hjkee]

Sorry,

In xilinx logiCore, I choose a wrong FPGA target  when I generate VHDL code.

Let me try to compile it with a new code.

*Updated*

Please ignore this message. It's compiled well with a new code.