6581 spec is 200Mb/s for DDR - can module design handle 480Mb/s DDR for LVDS?

[DiagSon]

The Virtex 5 devices can handle higher than 200Mb/s for DDR.

We're looking for minimum of 480Mb/s via LVDS streams into the Virtex de-serializer.

Can the boards and the adapter module interfaces handle these rates?

My guess is yes based on the Averna IEEE1394b Adapter.

[Ryan_V[DE]]

Hello DiagSon,

While the NI 6581 can't maintain these rates, you should certainly be able to build your own module capable of them. Here is an excerpt from the specifications document which should be live on the web very soon:

Maximum I/O data rates

Single-ended ...............................400 Mb/s for LVDCI25

Differential..................................1 Gb/s for LVDS

What kind of application do you have in mind?

Thanks,

Ryan

[DiagSon]

Thanks Ryan.

The application is as interface to a multichannel ADC that streams data as serial LVDS streams. Whilst we could put the ADC in the adaptor module the ideal would be to have it off-board so that we can stream in as LVDS.

The VHDL code for the de-serializer in Virtex5 is available from the ADC manufacturers so one follow-up question is going to be how easy this is to import into the socketed CLIP structure (we have experience with the standard RIO cards but not the VHDL side).

The other area of interest to us is how rapidly we can stream data out from (and also into) the FlexRIO card itself - either direct to/from the Virtex device or alteratively to/from the DRAM.

Cheers

Dave

[Ryan_V[DE]]

Hi Dave,

Very interesting application. I'm just curious, but is there a reason that you don't want to put the ADC directly on the adapter module? I can't comment on the specific IP you've acquired, but this tutorial should give you a good idea of how easy it is to import the IP. As for your second question, are you referring to streaming in and out of the front connector, or over the PXI backplane? The PXI-795x specifications are now live, and from those we see the I/O data rates quoted above, but also that the maximum theoretical memory bandwidth is 800 MB/s per bank times two banks. As for the PXI backplane, it is based on 32-bit, 33 MHz PCI, which has a maximum bandwidth of 132 MB/s. Since it is a shared bus, though, performance can be dependent on other traffic. We're looking at benchmarking this a little more thoroughly, so hopefully we'll have some more concrete numbers for you soon.

Regards,

Ryan

[DiagSon]

Hi Ryan

One of our applications requires the ADCs to be remote and so this was the reasoning for looking at this approach first. We had also thought that an LVDS receiver module would be a more universal requirement and so might be more likely to be available as a "generic" adaptor module.

Thanks for the link to the CLIP Node tutorial. I'll need to digest this and work out implications/constraints on the third party de-serializer code.

Our prime requirement is for acquisition of data which is then processed in the Virtex 5 before being streamed out via the backplane. Our previous application used the PXI-5105 but we'd run into driver problems that limited our overall transfer rate where the packet size was relatively small, hence the query about the overall rate.

Once acquisition is over, we would like to be able to use the FPGA as a separate resource for parallel processing of the acquired data and therefore the transfer rate back into the board is also of interest. I see from Fig 3 in the FAQs that the route from the PXI backplane to the DRAM is via the Virtex 5 device and so the transfer rate from backplane to/from DRAM won't be any faster than from backplane to/from Virtex.

Regards

Dave

[dial]

Hi Ryan.

We have similar application. The relevant de-serializer code is outlined in the Xilinx application note XAPP866 (see http://www.xilinx.com/support/documentation/application_notes/xapp866.pdf). It seems logical to use the ISERDES component and regional clocking on the Virtex 5  How easy would it be to integrate that (especially the clocking) via the CLIP node without much VHDL experience?

Regards

Dial

[Ryan_V[DE]]

Hello Dial,

This is a really tough question to answer. Aside from simply clocking in data, is there anything else you plan on doing in the CLIP? At what serial data rate do you plan to run? What kind of hardware do you have in mind? I'm afraid I can't assess your VHDL ability, but this should be a relatively straightforward task for an experienced designer.

Regards,

Ryan

[dial]

Hi Ryan

The Socketed CLIP would just be used to pull the data in and do the de-serializing. That's the bit that has the externally supplied VHDL code. The only additional requirement is for the FlexRIO FPGA to generate the LVDS clock stream out to the ADC. Once the data is back in parallel form, the whole of the rest of the processing would be done using standard LabVIEW FPGA graphical programming.

The aim is to start with a dual channel 12bit ADC sampling at 50MSPS, so the pair of DDR streams would be clocked in at 6x50MHz = 300MHz. There is the longer term possibility of going up to 80MSPS sampling (i.e. 480MHz DDR clocking) and up to 8 channels ADCs.

We would need to do a custom Adapter Module for this but one possibility would be to start at a lower clock rate to debug the code in which case we could use the NI6581 High Speed Digital Adapter Module which I understand would limit us to 100MHz/6 = 16.7MSPS conversion. The product info on the website says that this is available early 2009. Do you have any info on schedule for this?

Regards

Dial

[BrowningG]

Hello Dial,

With the NI 6581, it will be possible to get 200 Mb/s per channel using DDR at a 100 MHz output frequency. 

It is certainly possible to create a clock on your FPGA that can be used to provide a clock to your ADC.  I would suggest comparing the jitter and other specifications of the FPGA generated clock against the nominal specs of your intended ADC.  Depending on the clock specifications you need, you might consider using an external clock circuit on your adapter module if you have restrictions on your clock that are tighter than the FPGA clock specs.  Again, this is up to your design constraints. 

Regards,

BrowningG

[Raajit_Lall]

Hey Dial,

At this point we do not have a precise date on the release of the 6581 adapter module.  If you have an immediate and specific need, please feel to contact me offline at raajit.lall@ni.com and we can discuss this further.

Looking forward to hearing from you.

Best Regards,

Raajit