Community Browser
cancel
Showing results for 
Search instead for 
Did you mean: 

These are a few of our favorite things … about the LabVIEW NXG FPGA Module

This fall’s LabVIEW NXG update marks our first ever release of the LabVIEW NXG FPGA Module, and we couldn’t be more excited about it. While support for some of our most popular FPGA-enabled hardware is still forthcoming (we’re looking at you, CompactRIO), FlexRIO and USRP (Universal Software Radio Peripheral) users can try out the module today! See the full list of supported hardware here.

 

Here are our favorite LabVIEW NXG FPGA Module features, which we think you’re going to love. 

 

SystemDesigner

 

SystemDesigner isn’t necessarily a new feature; it’s been a part of LabVIEW NXG since the beginning. However, we love how intuitive it is for designing FPGA-based systems. We know that it can be challenging to keep track of all your system components and understand how they interact with each other. For example, when designing a new system, you need to keep track of all your targets and ensure proper data communication between them. You also need to configure and organize your FPGA resources, such as FIFOs, clocks, and memory, as well as ensure that your design is appropriately documented. You can use SystemDesigner to do all of this in one place, which helps you architect and visualize your entire system as a system.

 

fgpa.pngFigure 1: LabVIEW NXG uses SystemDesigner to help you intuitively organize your FPGA system

Clock-Driven Logic

 

If you’ve built high-throughput FPGA systems in LabVIEW, you’re probably familiar with the single-cycle timed loop structure. The ability to execute blocks of logic within a single clock cycle is part of what makes FPGAs so important for applications that require serious data throughput. However, it’s not always clear what functions can be used in a single-cycle timed loop. The LabVIEW NXG FPGA Module has made this clearer by creating a separate document type called Clock-Driven Logic, so you can tell which functions are supported in clock-driven execution.

Sampling Probes

 

We know the frustration of spending lots of time compiling FPGA code, only to discover an implementation error that you should have caught earlier on. One of our goals for the LabVIEW NXG FPGA Module is to improve workflows for simulation and debugging, empowering you to catch errors earlier and decrease the number of compilations you need to do.

 

In this first version of the LabVIEW NXG FPGA Module, we’ve added cycle-accurate sampling probes with an intuitive interface so you can more easily see how your code will operate over multiple clock cycles. In future releases, we will add even more simulations and debugging tools, so keep an eye out!

 

And More…

 

The LabVIEW NXG FPGA Module is all about smoothing the development workflow. In addition to the major features above, we’ve added others that we think will make your programming experience even more enjoyable. For the LabVIEW FPGA nerds out there, here are some of the little things you might be excited about:

 

  • Cluster support for DMA FIFOs
  • Save and replicate configurations for new designs using FPGA Resource Collections
  • Use the search function to locate FIFO entry and exit points on the block diagram
  • New complex fixed-point data types
  • Support for multi-dimensional arrays

 

 

3.pngFigure 3: FPGA Resource Collections make it easier to configure and duplicate your resources such as clocks, FIFOs, and memory

 

Overall, we’re excited to continue delivering a faster, easier approach to FPGA programming, which we have been doing since the inception of LabVIEW FPGA in 2003. With the LabVIEW NXG FPGA release, we hope to make your job even easier.

 

 

To try out the LabVIEW NXG FPGA Module for yourself, download the evaluation software.

 

 

 

 

Comments
Member

Looking forward to this, come on cRIO FPGA then we can properly jump onto NXG!