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EIA Electronics and Semiconductor Finalists


The Engineering Impact Awards invite engineers, scientists, and researchers from around the world to submit impactful applications created with our software and hardware. The annual event showcases an impressive collection of applications to highlight the impact these projects have on Electronics and Semiconductor.


Find out more about this year’s outstanding finalists:


A Highly Parallel Parametric Test System for In-Fab Wafer Test



Bart De Wachter, Kristof Croes



imec wanted to manage yield drops, optimize the R&D process flow, reduce costs, and decrease the time to market of the newest chip manufacturing techniques. How did the company do it? By performing accurate wafer-level parametric tests in the semiconductor fabrication process flow to detect process - related issues at an early stage. 


Testing devices from one probe pad module is usually completed in a sequence, one at a time, with a lot of switch operations in between. This process is time consuming since one chip can contain dozens of process control monitor modules. 


imec used numerous PXIe-4135 femtoampere-class source measure units (SMUs), in an SMU-per-pin parallel architecture, and build a highly parallel, PXI-based wafer-level parametric measurement system. The team used LabVIEW to synchronize and control the instrumentation, probe station, and automatic wafer loader and then recorded, analyzed, and logged the resulting measurement data.


With the new in-fab ATE solution, imec can perform experiments that were previously impossible or that came at a high wafer count cost. The new system has reduced the project cycle time from one month to three days, decreased the wafer loss from our four wafers down to one wafer, and cut the overall wafer process cost by 75 percent.



Package-Level PMIC Automated Test With Independent Smart Triggering


Samsung Electronics

In-Kook Yoon, Yun-Hui Han, and Kwang-Yoon Lee


Samsung - Stock Electronics Image.JPG

To improve the chip design and system stabilization of mobile devices, Samsung built a highly parallel test system for automated characterization and validation of increasingly complex power management IC's (PMIC's) for mobile electronics. 


The previous verification method compared event-based operation results in specific scenarios based on the performance indicators of PMIC's. These results were mainly verified at the IC level, but verifying all operations of the final mobile device through this method was difficult. It was impossible to predict all events, including whether a specific PMIC operation would affect other IC's in the actual operation and where this would happen. Examples of this included verifying the result of PMIC inputs/outputs according to specific operation conditions like playing videos, surfing the web, and making phone calls. Therefore, Samsung needed to verify not only the overall operation of PMICs in the final device but also their specifications. 


Samsung researchers compiled and defined the impact of unintended signals and faults by independently triggering and simultaneously measuring the response of 120 PMIC outputs using numerous PXIe-5172 oscilloscopes, an FPGA co-processing module, and a high-capacity RAID array. 


A manual test usually takes more than one month, but Samsung received its test results in three days using NI's automated test solution. Saving time led to precise data analysis, decreased time to market, improved employee satisfaction, and reduced engineer workloads. 


Learn more about the other 2019 Engineering Impact Awards Finalists:

Can't make it to the award ceremony? Watch the livestream here