We have been building on 2 examples from the NI Developer Zone in order to create a program using the FlexRio that can sample multiple FPGA inputs into various buffers using the 7954R and the 5751 adapter and transfer the buffers to the host machine using DMA FIFO.
We are having a couple of problems possibly steming from our trigger logic. The analog trigger we are using is supposed to only trigger on a falling edge as seen below. This trigger logic was taken from an example found here http://zone.ni.com/devzone/cda/epd/p/id/5819. The exact program is located under customtrigfpga8.zip>FPGA VIs>AnalogEdge.vi.
We begin by nesting our Trigger logic inside a flat sequence structure passing an initial value to a shift register in our loop. This initialization value is set to the lowest possible value we could receive from our ADC in order to prevent a false trigger of our system. This shift register is then compared with a user defined trigger level to see if it is greater than the trigger. Upon the first iteration of the loop this will be false. Next it compares the input from the adapter module with the user set Trigger Level to see if the input has fallen below the trigger level and passes the analog input value to the shift register. The contents of the shift register will then be compared with trigger level upon the next iteration. This confirms that we can only recieve a trigger high when the signal breeches the trigger threshold on a falling slope. These two boolean values are fed to an and gate, if the output of the and gate goes high (successful trigger) the loop will terminate and the boolean high value will be passed to the trigger indicator in the next sequence of the VI.
However the trigger indicator always apears to be high once we recieve our first trigger. The trigger also appears to be reacting only to rising edges above 0 and will not work on signals below 0 when looking at its behavior in the Top Level FPGA program depicted below.
Here is how we are applying the trigger using the FPGA data collection program shown below. This is based on the example found here http://zone.ni.com/devzone/cda/epd/p/id/5819
Since the example is set up to use a digital input trigger we replaced the digital input trigger with the above Analog triggering scheme. We can not however confirm the function of the digital trigger in the origional code because we have only 1 VHDCI cable and cannot both apply an analog input and apply an external digital trigger at the same time.
Here is how we have the FPGA daq loop configured:
This VI will continuously overwrite a buffer untill a "true" is recieved at the select node. The case will then change to "Aquire post-trigger Samples" (seen below) and write an additional user selected number of samples to the buffer (in our case 1600 post trigger samples and 2000 total samples).
When the post trigger samples are collected the case will change to "Setflag" where the VI will set a boolean flag in a sub vi to true and store the last adress it wrote to in the buffer.
Running parallel to this loop is the DMA Send loop (below) that is constantly checking the the flag. Once the flag is set the loop will read the contents of the buffer into the DMA FIFO starting at the last adress written to. Once the DMA finishes transfering the data it resets the flag and the VI waits for another trigger.
Once the DMA finishes writing the waveform, it is read out of the DMA FIFO on the host machine. Here are our results with a 10Hz ramp pulse with a 1.5ms width :
The trigger activates at the correct frequency (which we have tested experimentally) keeping the waveform centered at a fixed location but it is clear that the order of pre and post trigger samples are not in the correct order. With 2000 samples total and 1600 post trigger samples we should observe the negative slope threshold crossing at the 400th sample. What we are observing now however is that the trigger is located at ~1425 and the waveform is truncated because the pre-trigger samples are not being displayed.
Any advice as to debugging or overall technique would be greatly appreciated.
I was in the process of setting up some support for this issue because I will have limited avaiability tomorrow and Thrusday due to an NI Event in Albuqueruque and I noticed that you have an existing Service Request #7378302 for the same issue.
I can see in the notes that you are currently working with our Application Engineer, Joey. I will call him tomorrow to get an update. Please let me know if you are not getting adequate support. I will help get the resources we need for this.
Thank you Nick. We will get someone to take a look at this and see what we can do to help get this straightened out.
Are you all thinking about coming to our Developer Days?
I would love to attend the Developer Days. When and where are they taking place?
Also Joey has been very helpful but we havn't quite been able to pin down the issue yet. He gave me a few things to try in order to track down the error so ill have the results this afternoon. If theres any additional details I should include in the post just let me know. I will also attempt to host the full project and supporting files on a third party site in order for others to get access.
So sorry we did not get this to you sooner but the event is taking place tomorrow, Thursday, in Albuquerque all day at the Nuclear Museum.
Here is the user trigger we have implemented
This is what happens when we set the post reigger samples to 400:
As you can see, 5 windows of 400 samples are being displayed. The farthest left is the furthest back in time and the farthest right is the present trigger.
We believe this is because the analog trigger is always high and it is bypassing the pre trigger sample state seen above. However, even when using the user trigger to get triggers the result is the same with no pre-trigger samples displayed.