I am recieveing a DMA FIFO timeout error when I attempt to implement 10 DMA target to host channels in the same host vi. I currently have 5 FlexRIO 7966-R FPGA modules that have 2 DMA transfer channels a peice. When I implemented my code with only 3 FPGAs (i.e. 6 DMA channels) I did not recieve this error even when I recieved DMA overflows.
Here is a depiction of one of my read loops:
50400 error is related to the timeout of fifo which should be in synchronous with the data elements we are taking and giving to and from the fifo modules.It is concerned with the number of elements with timeout values.change your time out value to the default and number of elements to the default 5000 while providing fpga time out as 0 or -1(if sctl using ).