problem with gated JK latch using NAND gates

[Shank747]

Hello,

I have been trying hard for several hours to fix this simulation but now i am quite sure that it's a bug or problem with Multisim.

I want to implement a gated JK latch with NAND gates only. It's a very simple thing but somehow it's getting impossible. The design is based on my textbook but doesn't work in Multisim. Also, i'm not sure how to set up a positive-edge triggered clock signal but i have managed to find a way based on my searches and it doesn't work at all.

Any advice or help would be greatly appreciated.

[Tayyab_R]

Hi,

I was able to get the circuit working by using gates from the TTL Family. I would suggest using these ones because they have internal connections to power and ground.

Modified file is attached.

Hope this helps.

[Shank747]

There was a mistake with your modified attachment in one of the SR latch gate inputs. I have fixed it and attached the correct circuit, together with the schematic from wikipedia. But the simulation simply refuses to work properly. I have researched extensively and found several other threads on this forum about MultiSim not being able to correctly simulate JK FlipFlops based on logic gates. I really believe that this is a major bug in the software itself. I have recreated the exact same circuit in LiveWire and the latter simulates the circuit perfectly, and the characteristic table obtained corresponds perfectly to that in my textbook.

I am honestly very disappointed that such a simple and basic logic design is not being correctly simulated in MultiSim 11. To verify if that was fixed in the newest version 12, i downloaded the latest educator's trial version 12 but the problem still persists. I wanted to buy the new version of MultiSim but seeing that a simple gated JK latch is too much for this software, i am losing faith. Honestly, i don't know if i can trust this software to simulate anything else. Please advise!

[Tayyab_R]

Hi,

I was able to get the simulation running. It seems that since there was no resistor on the output, it was causing unexpected changes in current. I have replaced the buzzers with LED's along with a resistor and now the output is more realistic.

Please take a look at the attached file.

Hope this helps.

[Shank747]

Hi Tayyab,

Unfortunately, your suggestion does not work properly, as the ouput LEDs remain in permanent "toggle" states irrespective of the logic inputs. Please find attached the truth table for a positive edge-triggered JK flipflop. J and K are the logic inputs. C is the clock signal input. Q and Q' are the designated ouputs as shown in the Multisim circuit.

It really is the most basic JK flip flop circuit. I truly believe that it is some serious bug within Multisim itself, as i cannot think of anything else that might be wrong with the circuit, especially since the latter operates perfectly when designed and simulated in other electronic simulation softwares.

[OStep]

Shank747,

The shown design of a JK flip flop does not work in practice for J=K=1 state. Multisim is simply confirming this!

In order for it to work (i.e be stable and not oscillate as you're experiencing) the clock pulse width must be shorter than the delay of CLK-to-Q path (delay through two NAND gates). To complicate things it must be longer than then minimum delay of any of the gates, otherwise the pulse will be "swallowed" by the inertial delay effect.

Attached is a working version of the case where J=K=1. Note that it only works because I set clock pulse width to16ns which is in between the 15ns minimum delay and 30ns maximum path delay. Run transient analysis and you'll see Q toggling. If you use interactive switches, you'll have to be really quick (and accurate) with your hands to ensure the CLK pulse width meets the requirements.

This page discusses this:

http://www.electronics-tutorials.ws/sequential/seq_2.html

You'll need the master-slave design in the JK flip flop if you want to avoid the above problem.

Thanks