Multisim and Ultiboard

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Teardrops and design rule errors

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I recently completed a design and placed an order for PCB's.  The DFM came back with too close spacing violation.  Turns out when I added teardrops some were placed extending into IC pads and violating the pad to pad spacing of adjacent pads.  No design rule error was found or reported.  I modified the teardrop to actually overlap and short to adjacent pads and still no design rule error was reported.

 

This is troubling.  Teardrops are just little copper area triangles that should be part of DRC error checking like anything else.

UB14.1 Win10 64b

 

teardrop violation.PNG

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It seems that it can be an issue with the software, I suggest to post this concern on the ideas exchange forum

 

https://forums.ni.com/t5/Idea-Exchange/ct-p/ideas

 

 

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