I am an instructor using the diligent basys 3 board for teaching an introductory class on digital logic and PLDs. I am using the student version of multisim and Xylinx Vivado 2019.2 64bit. I am trying to use the schematic entry found in Multisim's PLD design module. I enter everything and then select Transfer>Export to PLD>Generate and Save PLD file option..... I then hit "finish" and I get the following error message:
Multisim - 2020年5月20日, 10:53:33
PLD topology check [Programmable Logic Device 2] - 2020年5月20日, 10:53:33
Completed; 0 error(s), 0 warning(s), 0 filtered error(s); Time: 0:00.00
PLD Export [Programmable Logic Device 2] - 2020年5月20日, 10:54:50
Selected tool: Xilinx Vivado Design Suite 2019.2 64-bit (Unsupported) (User specified at: D:\Vivado\Vivado\2019.2\)
****** Vivado v2019.2 (64-bit)
**** SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019
**** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
source {C:\Users\Miss Bear\AppData\Local\Temp\NiCds\pld_export_2\viv660F.tmp}
missing close-brace
while executing
"create_project -force vivado_project {c:/users/miss bear/appdata/local/temp/nicds/pld_export_2/vivado_project{ -part xc7a35tcpg236-1
set_property targ..."
(file "C:\Users\Miss Bear\AppData\Local\Temp\NiCds\pld_export_2\viv660F.tmp" line 1)
INFO: [Common 17-206] Exiting Vivado at Wed May 20 10:55:03 2020...
Error: The current step failed. Export aborted.
Completed; 1 error(s), 0 warning(s); Time: 0:12.92
