Problem with logic states (wrong multisim interpretation?)

[Grimmrock]

Hi, I'm making a clock for my project (it has to be made from only logic gates, D flip flops, and of course 7 seg display) and I've got a little problem with logic states on the gates outputs, like on the attached picture (i know it's a little bit messy, but i was testing the outputs) as you can see, the signal is not reaching the lamp on the top, so it also can't reach "Reset" on 4bit counter made from D flip flops.

Can someone help me with my problem? I can send the whole project if it will be necessary.

[Grimmrock]

Another example of wrong multisim simulation click here