11-06-2007 05:01 AM
11-07-2007 05:27 PM
11-08-2007 03:41 AM
11-08-2007 08:56 AM
Please note that I'm no expert on that field, but my guess is that if you are trying to check the signal quality of a 50 Hz sinusiodal wave, you need to compare it to another 50 Hz sine wave that you know is "perfect". In order to accomplish this I would generate a pulse train whose rising events will be tied to a specific section of the input sine wave cycle, lets say, crossing 0 V from low to high. That is, the 0 V crossing would trigger an active high for my pulse train and then I can catch every single cycle of the input signal... this pulse train would be the signal for the PLL... the "perfect" sine wave is being generated perhaps in the FPGA but is synchronized via the PLL to the input sine wave using that pulse train that I'm talking about...
This would be my initial thought on how to attack that problem, I hope it helps.