PISO model, shift register 12bits

[grigmodel]

Hello,

I want to model a misc digital CI only for simulation in multisim. The functionality is PISO (parallel in/serial out) when TE input is high. 

Until now I made the spice model as bellow, but no working. Pls. help.

Symbol(ANSI)         Symbol(DIN)       
  

##################  Model  ##################

Model ID            : RegHT12E
Model manufacturer  : Generic
Model template      : 

a%p [%tP1?%t:d%t;P1
+      %tP2?%t:d%t;P2
+      %tP3?%t:d%t;P3
+      %tP4?%t:d%t;P4
+      %tP5?%t:d%t;P5
+      %tP6?%t:d%t;P6
+      %tP7?%t:d%t;P7
+      %tP8?%t:d%t;P8
+      %tPA?%t:d%t;PA
+      %tPB?%t:d%t;PB
+      %tPC?%t:d%t;PC
+      %tPD?%t:d%t;PD
+      %tTE?%t:d%t;TE
+      %tCLK?%t:d%t;CLK]
+      [%tOUT?%t:d%t;OUT] %m

Model data          : 

.MODEL RegHT12E d_chip  ( behaviour= "
+; HT12E
+/inputs TE CLK PD PC PB PA P8 P7 P6 P5 P4 P3 P2 P1
+/outputs OUT
+/clock CLK + 12 2 1
+;SYNC
+; TE CLKPDCBA87654321 FFFFFFFFFFFF  NF NF NF NF NF NF NF NF NF NF NF NF
+  L  X   XXXXXXXXXXXX XXXXXXXXXXXX  PD PC PB PA P8 P7 P6 P5 P4 P3 P2 P1
+  H  X   XXXXXXXXXXXX XXXXXXXXXXXX  L F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10
+;ASYNC
+; TE CLKPDCBA87654321 FFFFFFFFFFFF  NF NF NF NF NF NF NF NF NF NF NF NF
+  X  X   XXXXXXXXXXXX XXXXXXXXXXXX  F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11
+/table 1
+; TE CLKPDCBA87654321 FFFFFFFFFFFF OUT
+  X  X   XXXXXXXXXXXX XXXXXXXXXXXX F11
+/delay 2
+;input  output  Rise time  Fall time
+  TE    OUT      280n        300n
+  CLK   OUT      280n        300n
+/constraint 27
+;   Name       Event From  Event To   Min/Max  Time
+ 'PULSE WIDTH'  LH    CLK   HL   CLK    MIN     25n
+ 'SETUP'        HL    TE    HL   CLK    MIN     20n
+ 'SETUP'        LH    P1    HL   CLK    MIN     30n
+ 'SETUP'        LH    P2    HL   CLK    MIN     30n
+ 'SETUP'        LH    P3    HL   CLK    MIN     30n
+ 'SETUP'        LH    P4    HL   CLK    MIN     30n
+ 'SETUP'        LH    P5    HL   CLK    MIN     30n
+ 'SETUP'        LH    P6    HL   CLK    MIN     30n
+ 'SETUP'        LH    P7    HL   CLK    MIN     30n
+ 'SETUP'        LH    P8    HL   CLK    MIN     30n
+ 'SETUP'        LH    PA    HL   CLK    MIN     30n
+ 'SETUP'        LH    PB    HL   CLK    MIN     30n
+ 'SETUP'        LH    PC    HL   CLK    MIN     30n
+ 'SETUP'        LH    PD    HL   CLK    MIN     30n
+ 'HOLD'         HL    CLK   HL   TE     MIN     25n
+ 'HOLD'         HL    CLK   LH   P1     MIN     25n
+ 'HOLD'         HL    CLK   LH   P2     MIN     25n
+ 'HOLD'         HL    CLK   LH   P3     MIN     25n
+ 'HOLD'         HL    CLK   LH   P4     MIN     25n
+ 'HOLD'         HL    CLK   LH   P5     MIN     25n
+ 'HOLD'         HL    CLK   LH   P6     MIN     25n
+ 'HOLD'         HL    CLK   LH   P7     MIN     25n
+ 'HOLD'         HL    CLK   LH   P8     MIN     25n
+ 'HOLD'         HL    CLK   LH   PA     MIN     25n
+ 'HOLD'         HL    CLK   LH   PB     MIN     25n
+ 'HOLD'         HL    CLK   LH   PC     MIN     25n
+ 'HOLD'         HL    CLK   LH   PD     MIN     25n
+")
.end


##################  Package  ##################

Footprint: 
Footprint not found in Ultiboard Database

Package type        : 
Package manufacturer: Generic
Pin Count           : 15

Pins information    : 
Logical  Physical  Section  Type                ERC Status  Pin Swap Group  Gate Swap Group
P1                 GRP:A    D:INPUT:TIL_RCV     INCLUDE                                    
P2                 GRP:A    D:INPUT:TIL_RCV     INCLUDE                                    
P3                 GRP:A    D:INPUT:TIL_RCV     INCLUDE                                    
P4                 GRP:A    D:INPUT:TIL_RCV     INCLUDE                                    
P5                 GRP:A    D:INPUT:TIL_RCV     INCLUDE                                    
P6                 GRP:A    D:INPUT:TIL_RCV     INCLUDE                                    
P7                 GRP:A    D:INPUT:TIL_RCV     INCLUDE                                    
P8                 GRP:A    D:INPUT:TIL_RCV     INCLUDE                                    
PA                 GRP:A    D:INPUT:TIL_RCV     INCLUDE                                    
PB                 GRP:A    D:INPUT:TIL_RCV     INCLUDE                                    
PC                 GRP:A    D:INPUT:TIL_RCV     INCLUDE                                    
PD                 GRP:A    D:INPUT:TIL_RCV     INCLUDE                                    
TE                 GRP:A    D:INPUT:TIL_RCV     INCLUDE                                    
CLK                GRP:A    D:INPUT:TIL_RCV     INCLUDE                                    
OUT                GRP:A    D:OUTPUT:TIL_DRV    INCLUDE                                    

[_user32]

grigmodel

The d_chip digital behavior model is very powerful - and I've created some shift register models from it (I have a HCT595 somewhere on my PC)... but it can be tricky to work with.

If you are not aware, there is a d_chip guide that our R&D team was working on - I would go through the d_chip document that was posted in a previous forums page last year...

http://forums.ni.com/t5/Circuit-Design-Suite-Multisim/models-using-d-chip/m-p/953453

If you can still not determine the behavior please reply back and I will dig into your specific model more.

Regards,

Patrick Noonan
Business Development Manager
National Instruments - Electronics Workbench Group

[grigmodel]

    Thanks. I solved.
There was an inconsistency between chip circuit order params and model template.

    The d_chip guide is very valuable. I used that guide to model other complex chips. The problem with the guide are the lack of examples and almost no description of /constraint section for PULSE WIDTH, SETUP, HOLD...

    The shift register 12 bits spice model served as circuit part of Holtek 12 bits encoder HT12E.
    If anyone interested, now I have available, for free!, multisim models for HT12E and HT12D (decoder), cmos 4067, for simulation and layout, and other helper chip models for simulation only (CMP8= compare 8 pair gates, PIPO4STORE= PIPO 4 bit storage, SIPO12= register).

Best regards,

Grig

[_user32]

Grigmodel,

That's great!  Yes please post the models for the benefit of all users...

I will check to see with our R&D team to see if there has been any updates to the d_chip guide that was posted last year.

Thanks!

Pat Noonan

National Instruments

[OStep]

Yes we added documentation for the syntax for the d_chip device. Under Multisim Help, go to Simulation->Multisim SPICE Reference->Digital and Mixed mode device library->Digital Chip->

Thanks

[grigmodel]

Hello,

   4067, HT12E, HT12D models. Included in archives: chip's docs, simulation models and schematic examples.

Best regards,

Grig

[grigmodel]

Screenshots for HT12 simulation in attachments.

[grigmodel]

In attachments there are steps to create HT12E and HT12D (Holtek encoder and decoder) for NI ver. 10. Can be adapted to other NI ver.

[stuti_3001]

where can i find the HT12E encoder?? please help me with it