Offset problem in simulating current and voltage phase relation of parallel rlc circuit, Is it a bug ?

[yyao]

Try this:

1. Click Simulate>>Interacitve Simulation Settings
2. For Initial conditions, choose User-defined
3. Click OK
4. Restart interactive simulation

[bangkaew]

Thanks Yyao,  it works now.

Just wonder how many people know that  

.... current and voltage phase relation of inductor is derived from current as input and voltage drop as output, when you reverse the cause and effect , the result may not be the same.

Most textbooks and websites are unaware of this offset problem for pure inductor,

[Just_Plain_Bob]

Y

I had somewhat similar problems for slightly different circuit parameters. To quote your peer Tien

"The model of an inductor is essentially a voltage source and when you have
two voltage sources in parallel you create an conditions known as "voltage
loop", .....  This issue is not unique to Multisim and it is an issue with any SPICE simulator."

Switching to a current source like was done above may have been a solution.

Lastly, in the past someone at NI suggested the offset might be due to integration method.

[yyao]

Hi Bob,

Thanks for sharing this with us!

[bangkaew]

Thank you for your interests in the problem, Below is my opinion.

In real world, the pure inductor does not exist,  its inductance L  is always in series with its small resistance R, so there is a time constant = L/R to consider before it reaches steady state.  For  the case of pure inductor, R=0  that makes Time Constant becomes infinite, and the offset left forever.

My suggestion is that if you are interested in only  the result for the steady state , other method should be used instead of numerical integration.

[anm]

thanks