Multisim 14: FET component wizard error

[tamsdon]

Dear All,

I am having an issue with an ON semi model for a FDG1024NZ FET. I have downloaded the .lib file from the ON semi website, and used the Component Wizard in Multisim. I have created a 4 pin symbol for the device (based on post in this community stating that a 4 pin device should be used for a 3 pin subcircuit). When I attempt to advance the wizard page form for the model data, it incurs the following error:

"SPICE Netlist Error, element 'Bsim3:FDG1024NZ': Unsupported model type 'NMOS'
SPICE Netlist Error, element 'M_BSIM3:FDG1024NZ': Unsupported SPICE device type 'MOS7'
Do you want to continue?"

Is there anyone who can give me advice on how to import the NMOS and MOS7 models, and/or whether I need to modify the listing shown below.

Many Thanks!

.SUBCKT FDG1024NZ 2 1 3
******************************************************************
** Fairchild Discrete Modeling Group **
******************************************************************
** Website www.fairchildsemi.com\models **
** Scott Pearson scott.pearson@fairchildsemi.com **
** Chris Hanas chris.hanas@fairchildsemi.com **
******************************************************************
** (C) Copyright 2009 Fairchild Semiconductor Corporation **
** All rights reserved **
** **
** FDG1024NZ Spice model **
** Revision RevA, 17 Nov 2009 **
******************************************************************
*Nom Temp 25 deg C
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Lgate 1 9 0.474e-9
Ldrain 2 5 0.1e-9
Lsource 3 7 0.547e-9
RLgate 1 9 4.74
RLdrain 2 5 1
RLsource 3 7 5.47
Rgate 9 6 2.17
It 7 17 1
Ebreak 11 7 17 7 22.5
Rbreak 17 7 RbreakMOD 1
.MODEL RbreakMOD RES (TC1=0.75e-3 TC2=-0.4e-6)
.MODEL DbodyMOD D (IS=0.2e-12 n=0.9 RS=205e-3 TRS1=2e-3 TRS2=1e-6
+ CJO=0.04e-9 M=0.6 TT=1e-9 XTI=1)
.MODEL DbreakMOD D (RS=30e-3 TRS1=1e-3 TRS2=1e-6 )
Rsource 7a 7 43.915e-3
Rdrain 5 16 RdrainMOD 91e-3
.MODEL RdrainMOD RES (TC1=3.6e-3 TC2=5e-6)
M_BSIM3 16 6 7a 7a Bsim3 W=0.12 L=1.05e-6 NRS=0 NRD=0
.MODEL Bsim3 NMOS (LEVEL=7 VERSION=3.1 MOBMOD=3 CAPMOD=2 paramchk=1 NQSMOD=0
*Process Parameters
+ TOX=240e-10 ;Oxide thickness
+ XJ=0.52e-6 ;Channel depth
+ NCH=1.32e17 ;Channel concentration
*Channel Current
+ U0=870 VSAT=200000 DROUT=2.5
+ DELTA=0.01 PSCBE2=0 RSH=43.915e-3
*Threshold voltage
+ VTH0=0.87
*Sub-threshold characteristics
+ VOFF=-0.1 NFACTOR=1
*Junction diodes and Capacitance
+ LINT=0.18e-6 DLC=0.18e-6
+ CGSO=720e-12 CGSL=0 CGDO=0e-12 CGDL=900e-12
+ CJ=0 CF=0 CKAPPA=1
* Temperature parameters
+ KT1=-0.6 KT2=0 UA1=11e-9
+ NJ=10)
.ENDS FDG1024NZ

[Gaheel17]

Hi tamsdon,

I found this forum, it is almost the same issue as yours. You can take a look at it for more detail explanations, but it seems that the solution was to modify the SPICE model as follows:

.SUBCKT FDG1024NZ 2 1 3

******************************************************************

** Fairchild Discrete Modeling Group **

******************************************************************

** Website www.fairchildsemi.com\models **

** Scott Pearson scott.pearson@fairchildsemi.com **

** Chris Hanas chris.hanas@fairchildsemi.com **

******************************************************************

** (C) Copyright 2009 Fairchild Semiconductor Corporation **

** All rights reserved **

** **

** FDG1024NZ Spice model **

** Revision RevA, 17 Nov 2009 **

******************************************************************

*Nom Temp 25 deg C

Dbody 7 5 DbodyMOD

Dbreak 5 11 DbreakMOD

Lgate 1 9 0.474e-9

Ldrain 2 5 0.1e-9

Lsource 3 7 0.547e-9

RLgate 1 9 4.74

RLdrain 2 5 1

RLsource 3 7 5.47

Rgate 9 6 2.17

It 7 17 1

Ebreak 11 7 17 7 22.5

Rbreak 17 7 RbreakMOD 1

.MODEL RbreakMOD RES (TC1=0.75e-3 TC2=-0.4e-6)

.MODEL DbodyMOD D (IS=0.2e-12 n=0.9 RS=205e-3 TRS1=2e-3 TRS2=1e-6

+ CJO=0.04e-9 M=0.6 TT=1e-9 XTI=1)

.MODEL DbreakMOD D (RS=30e-3 TRS1=1e-3 TRS2=1e-6 )

Rsource 7a 7 43.915e-3

Rdrain 5 16 RdrainMOD 91e-3

.MODEL RdrainMOD RES (TC1=3.6e-3 TC2=5e-6)

M_BSIM3 16 6 7a 7a Bsim3 W=0.12 L=1.05e-6 NRS=0 NRD=0

.MODEL Bsim3 NMOS (LEVEL=8 VERSION=3.1 MOBMOD=3 CAPMOD=2 paramchk=1

*Process Parameters

+ TOX=240e-10 ;Oxide thickness

+ XJ=0.52e-6 ;Channel depth

+ NCH=1.32e17 ;Channel concentration

*Channel Current

+ U0=870 VSAT=200000 DROUT=2.5

+ DELTA=0.01 PSCBE2=0 RSH=43.915e-3

*Threshold voltage

+ VTH0=0.87

*Sub-threshold characteristics

+ VOFF=-0.1 NFACTOR=1

*Junction diodes and Capacitance

+ LINT=0.18e-6 DLC=0.18e-6

+ CGSO=720e-12 CGSL=0 CGDO=0e-12 CGDL=900e-12

+ CJ=0 CF=0 CKAPPA=1

* Temperature parameters

+ KT1=-0.6 KT2=0 UA1=11e-9

+ NJ=10)

.ENDS FDG1024NZ

Try it and let us know if it worked.

Regards,

Jose F.

[tamsdon]

Dear Jose F.

Thank you. I am very grateful for your assistance. I have just setup the part in Multisim part wizard and the spice model was now accepted. I will do more testing later tonight.

I am also having a similar issue with the following Intersil part, can you provide an insight with this file?

If I can help you with modelling issues in future, please contact me.

Best Regards,

tamsdon

*ISL55110 Spice Model
"* Revision F, Aug 2008"
* Delays now simulated with Delay Lines instead of RC Time Constants
* Models
*$
.model SWOUTN VSWITCH ron=2.83 roff=100Meg von=+.2 voff=-.2
*$
.model SWOUTP VSWITCH ron=2.6 roff=100Meg von=.2 voff=-.2
*$
.model den D (n=1)
*$
.model SWMOD VSWITCH ron=10 roff=100Meg von=+.1 voff=-.1
*$
.model SWHIZ VSWITCH ron=100Meg roff=0.001 von=+.2 voff=-.2
*$

* Components Definitions
*Input PAD
.subckt IN_PAD 1 2
RIN  1  2  100e6
CIN  1  2  1e-12
.ends
*$
* Output PAD (IN GND)
.subckt OUT_PAD 1 2
RIN 1  2  100e6
* CIN should be adjusted  depending on the power down time.(PD time - 10 ns )
CIN 1  2  14e-12
.ends
*$
*Comparator with hysterisis
*COMP_HS IN OUT VDD GND
.subckt COMP_HS 1 2 3 4
* Thresholds
VTHR1 7 4 1.2
VTHR2 8 4 1.4
* VDD/2 Generation
R1 3 9 100e6
R2 4 9 100e6
*Delayed output
R3 2 21 3e3
C1 21 4 0.43e-12
SW1 7 10 21 9 SWMOD
SW2 8 10 9  21 SWMOD
*COMPARISON
SW3 3 2 1 10  SWMOD
SW4 4 2 10 1  SWMOD
.ends
*$
* Buffer Models ( IN OUT VDD GND)
.subckt BUF_X 1 2 3 4
*Generating VDD/2
R1 3 7 100e6
R2 4 7 100e6
SW1 3 2 1 7 SWMOD
SW2 4 2 7 1 SWMOD
.ends
*$
*Level shifter (IN OUT LV_SUPPLY GND HV_SUPPLY)
.subckt LS 1 2 3 4 5
*Gnerating VDD/2
R1 3 7 100e6
R2 4 7 100e6
SW1 5 2 1 7 SWMOD
SW2 4 2 7 1 SWMOD
.ends
*$
* Delay from LV(VDD) components in signal path
* LV comparator and level shifter give a delay of 3 ns(approx).
* T=0.69*R*C Obsolete, use delay line model instead
* Delay_LV IN OUT GND
.subckt Delay_LV 1 2 3
T1 1 3 2 3 Z0=100Meg TD=3n
R1 2 3 100Meg
*C1 2 3 0.43e-12
.ends
*$
* Delay from HV inverters in the signal path.
"* though this delay vary with supply(VH) , modeled delay as 6 ns ."
* T=0.69*R*C Obsolete, use delay line model instead
.subckt Delay_HV 1 2 3
T1 1 3 2 3 Z0=100Meg TD=6n
R1 2 3 100Meg
*C1 2 3 0.43e-12        
.ends 

*$
.subckt DelaY_HV-1 1 2 3
T1 1 3 2 3 Z0=100Meg TD=3n
R1 2 3 100Meg
*C1 2 3 0.43e-12        
.ends       
*$
*ISL55110 model       
*       
*      VDD PD IN_B  IN_A  OA VH GND OB ENABLEZ   
*   |   |  |  |  |  |  |   |    |
*   |   |  |  |  |  |  |   |    |
*   |   |  |  |  |  |  |   |    |
*   |   |  |  |  |  |  |   |    |
*   |   |  |  |  |  |  |   |    |
*   |   |  |  |  |  |  |   |    |
*   |   |  |  |  |  |  |   |    |
*   |   |  |  |  |  |  |   |    |
*   |   |  |  |  |  |  |   |    |
*   |   |  |  |  |  |  |   |    |
*   |   |  |  |  |  |  |   |    |
*   |   |  |  |  |  |  |   |    |
.subckt ISL55110 1   2  3       4    5  6  7   8    9       
XPAD_INB  3  7 IN_PAD       
XPAD_INA  4  7 IN_PAD       
XPAD_PD   2  7 IN_PAD       
XPAD_ENZ 9  7 IN_PAD
*Input Clamp Diodes for IBIS
d5 7 3 den
d6 3 1 den
d7 7 4 den
d8 4 1 den
d9 7 2 den
d10 2 1 den
d11 7 9 den
d12 9 1 den
*
*
*       
R1 1 99 100e6       
R2 99 7 100e6       
R10 6 199 100e6       
R11 7 199 100e6       
XCOMP_A  4 10 1 7 COMP_HS       
XCOMP_B  3 11 1 7 COMP_HS       
XDELAY_LVA  10 12 7  Delay_LV        
XDELAY_LVB  11 13 7  Delay_LV       
XLEVEL_SHIFTERA  12 14 1 7 6  LS        
XLEVEL_SHIFTERB  13 15 1 7 6  LS        
XDELAY_HVA 14 16 7 Delay_HV
XDELAY_HVB 15 17 7 Delay_HV
*PD or ENABLEZ
R3 18 7 100e6
SW1 1 18 2 99  SWMOD
*SW2 1 18 9 99 SWMOD
SWA 16 19 99 18 SWMOD
SWB 17 20 99 18 SWMOD
V  210 7 -1
R4 19 210 100e6
R5 20 210 100e6
* OUTPUT SWITCHES
*OA Switch
T1 9 7 230 7 Z0=100Meg TD=15n
R6 230 7 100Meg
SWTPA 6 220 230 99  SWHIZ
*
SWPA 220 5 19 199  SWOUTP
SWNA 221 5 199 19    SWOUTN
*
SWTNA 7 221 230 99    SWHIZ
*
C1 5 7 100pF
d1 7 5 den
d2 5 6 den
XPAD_OUTA 5 7 OUT_PAD
*
*
* OB Switch
*HIZ High Side
SWTPB 6 222 230 99  SWHIZ
*
SWPB 222 8 20 199  SWOUTP
SWNB 223 8 199 20  SWOUTN
*HIX Low Side
SWTNB 7 223 230 99    SWHIZ
C2 8 7 100pF
d3 7 8 den
d4 8 6 den
XPAD_OUTB 8 7 OUT_PAD
.ends
 
*$

[Gaheel17]

Hi tamsdon,

Can you provide information about the error message you get when trying to load this SPICE model?

Regards,

Jose F.

[tamsdon]

Hi Jose F.

Thanks again for providing much appreciated assistance.

I am once again creating this component using the TOOLS->COMPONENT WIZARD. I have created simulation only model (no layout) and a schematic symbol with 9-pins as per the spice listing (see attached spice model .txt). I have also attached a .jpg file showing the error message that is displayed after I enter the spice listing into the component wizard at Step 5. The error message reads "Component Wizard Step 5 of 7: The model contains multiple top-level .subckt statements. Place any dependent .subckt or .model definitions within the main (top-level) .subckt".

Thanks again for your help.

tamsdon