Multisim 10 Netlist alterate data not passing correctly to Ultiboard 10

[kittmaster]

When in multisim, if you set the trace width, trace min and max when you transfer to ub it only acknowledges trace width and not passing min and max value during the import routine. If the values are present in MS, then the autoimport should be parsing the netlist file and DISPLAY the min max fields showing the user that that data is being passed correctly during imporation.

Next, the trace to trace > to pad > to via > and other when those fields are populated with values in MS the import routine is ub only show trace clearance none of the other values, again, if there is data in spreadsheet view in MS for specific values, that should be parsed and passed to UB which should be displayed in UB's import routine dialog verifying the data is making it in.

I've spent hours sorting this mess and found that extra options added for pcb control done in MS are NOT being propogated correctly to ub. This is a TOTAL WASTE OF TIME!

This leads to the question of why are the options there in ms if they are not being passed to ub?? Therefore all those options must be hard set in UB which means back and forth to see which nets need adjusting........one page design.....no problem, but multisheet 35 page design??.......um no way!!

I'm also seeing that there are conflicts and net collisions between ms and ub. If you have lets say vcc in MS set to 30 mil, min at 20 max at 40 and you pass that to ub, on only the 30 gets propogated, but UB chokes on the 20 and 40 value since it is attached to the net thereby when the autorouter runs, it has diverging directives and therefore does not route that net even if the components are an inch apart with nothing in the way!!!! The only fix to to drop the 20 and 40 is ms and reexport the list ..............took DAYS to figure it out........the root seems to be that ub doesn't import the 20 and 40 correctly causing partial return from the autorouter.....

Anyone else seeing this?

Chris

[Tien_P]

Using a sample file installed with Multisim, I was able to get this to work in my circuit.  The file is attached if you want to look at it.   I did see the problem for the min/max trace length that did not get transferred from Multisim to Ultiboard, but other settings worked in my test file.  The Trace >> trace, pad, via and copper are hard to see but they do get transferred to Ultiboard.  You need to turn on the “Use multiple clearances” option, this is under OptionàPCB PropertiesàDesign Rule.  If you turn on your clearance by select ViewàClearance, you will see two clearances, the brighter blue clearances are the trace settings.  I had to use the ruler to measure if this is the same size as what was set in Multisim.