Multisim and Ultiboard

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How do I model a phase-locked loop in Multisim9?

Euler's file is not a zip file. It is a Multisim 10 file. Just change the file's extention form .zip to .ms10 and it should load into Multisim 10 if you have it.
Kittmaster's Component Database

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Message 11 of 18

Tried the example for PLL in one of my experiments, guys let me know if it works or not. Enjoy

I updated my attachments with the experiment specs.

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Message 12 of 18

Here is the update of my example for the PLL with specs for the experiment, from my last post. Enjoy

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Message 13 of 18

Sorry guys my experiment circuit discription for VCO out was not correct, it was bassed on the free running internal frequency of 68.2khz, The internal free running frequency should be 25khz for the PLL to lock with 25Khz generator frequency. I Also included the non filter circuit in the example to show the difference in designs.

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Message 14 of 18

Updated the discription for the virtual pll zip circuit

Message 15 of 18

Can anyone tell me please how I could stop or block phase locked loop wireless signals ?

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Message 16 of 18

can u please attach the zip file again , its showing corrupted,

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Message 17 of 18

Can u send me the original Eule's identity Circuit, It seems to be damaged. Thanks

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Message 18 of 18