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How do I model a phase-locked loop in Multisim9?

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I'm desiring to model a phase-locked loop circuit.  As it stands, I have one option in Multisim9: PLL_VIRTUAL.
 
I'd much rather have some popular IC models to choose from, particularly the cd4046.  (Anyone out there have it for Multisim??  Yes, I've done the THS7001 component creation tutorial.  I still don't know where to start modelling the cd4046, and I have what appears to be a SPICE model for it too.  That tutorial, even though I took the time to do it, is still rather lackng.)
 
Anyway, I looked at the PLL_VIRTUAL symbol and it doesn't work or something isn't labelled correctly.
 
Here are the pins of the virtual model:
1.  PLLin
2.  PDin
3.  VCOout
4.  PDout
5.  LPFout
 
But here's what a PLL actually looks like:
 
1. fin  -- the signal being locked to (one input of the phase detector)
2. fref  -- the signal fed back from the VCO (or a divider) (the other input of the phase detector)
3. PDout -- the output of the phase detector, an average DC indicative of the phase difference between the two input frequencies
4. VCOin -- the control voltage input of the VCO -- without it the VCO is free running!
5. VCO (fref) creating components -- the (usually) R(s) and C(s) that setup the VCO's fo and frange 
 
In the Multisim model, I'm guessing I have but one LPF option, as it's requesting the cutoff frequency, and I'm guessing that it's a simple RC (as a lead-lag has two break f's.)  But what of a lead-lag filter or active LPF options?  Moreover, how does one feed a LPF out as a VCO control voltage when there is no VCOin??  Plus, what's the point of seeing a LPF out?  That's what Multisim's for, to model (at least) RC LPF circuits, right??
 
Plus the brief description wasn't helpful either.  I know how a PLL works, just not how Multisim models one.
 
I guess what I'm looking for here is:
1. A Multisim model for a cd4046  (ideally) and/or
2. A virtual model for a PLL that makes sense, and, if possible,
3. options besides a simple RC for the LPF, the heart of a successful PLL design
 
Surely someone out there has tried to simulate a PLL in Multisim, right?  I sure could use your help!
 
Thanks! 
 
 
  
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Message 1 of 18
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One possibility I've thought of, which should be doable, is to build my own model/circuit piecemeal and then make it a subcircut.  I'm pretty sure Multisim has a VCO, and then the phase detector could be duplicated from the real McCoy.  Then, of course, the rest is a given.

But it'd be great if I coud find a model...

  

Message 2 of 18
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Well, I'm glad I didn't wait around...

Answer:

To model a phase locked loop in Multisim requires building the phase locked loop components on your own: the phase detector, the loop filter, and the VCO.  For the VCO use the virtual voltage-controlled voltage source (VCVS).  The loop filter is a given, just R and C and, perhaps, an op amp (a saturating one!).  The phase detector schematic, at least the one I wanted (PD II), is available via Fairchild or a more esoteric one is available via Texas Instruments app notes.

However, via the TI app note for the 4046/7046HCT..., I found two equations and two unknowns for designing the loop filter after a few givens.  So, rather than complete the Multisim simulation, I went to Excel, after manipulating the equations a little to get the two time constants I needed, and walla now I have a working PLL, and it worked beautifully the first time.  Hence, maybe if I have tme, just for the heck of it, I'll (try to) simulate it.  The hard part was the loop filter; I only wanted to simulate the PLL because I couldn't find good information on the loop filter design, but now I have it.

 

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Message 3 of 18
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Here's a working pll I created.  I thought it was neato and thought I'd pass it along.

Just change the suffix to .ms10 from .zip.

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Message 4 of 18
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Great, thanks for sharing.

Gosh, I whish NI would go all the way with EWB as it is still needing improvements.

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I would like to add something to this post that I think may be useful. I am going to post a circuit that I created using the Virtual PLL that no one, including myself, knew how to hook-up. I was examining  Euler's Identity's circuit and tried to hook up the Virtual PLL based upon his connections. I came up with the following circuit. It seems to work, but I will let you all  examine it and see if I am correct in my assumption.

If it is working properly, then all the credit for figuring this out should go to Euler's Identitiy because without his circuit I wouln't have been able to come up with my circuit.

Here it is:

Kittmaster's Component Database
http://ni.kittmaster.com

Have a Nice Day
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Message 6 of 18
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I must make a correction to my circuit I posted. On further review of Euler's circuit, I believe I made a connection error on the ouput. The scope should be tied to the VCO out terminal instead of the LPFout.  Sorry if that caused any problems for anybody.
 
Have a Nice Day
Kittmaster's Component Database
http://ni.kittmaster.com

Have a Nice Day
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Message 7 of 18
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Hi Lacy,
 
I tried it, it does not seem to work. It appears to me as if this PLL model is an analog PLL.
 
I'd love to see a digital one modeled after the 4046 chip.
 
Eulers discrete digital PLL works fine as is.
 
I really whish NI would pick up on his work and quickly come up with a better solution.
 
Cheers
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Message 8 of 18
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The reason it doesn't seem to be working is that I had the scope on normal. If you put it to auto, then it should show an ouput signal. If you wouldn't mine trying that and let me know if works then I would greatly appreciate that.

You are probably right about it being analog. I tried a square wave and the signal was all distorted. Anyway, I tried and we have Euler's Circuit that we can use to create a component if we need to.

Thanks and Hava a Nice Day

Kittmaster's Component Database
http://ni.kittmaster.com

Have a Nice Day
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Message 9 of 18
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Hi everybody, I need help to get the file of the Euler, I try many times to downlod but always the zip is damaged.
please send me a copy of the file to  davidhvm at hotmail dot com
 
I try to contact somebody but I can find the way to do.
Thanks
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