How do I model a phase-locked loop in Multisim9?

[lacy]

Euler's file is not a zip file. It is a Multisim 10 file. Just change the file's extention form .zip to .ms10 and it should load into Multisim 10 if you have it.

[Michael Arnold]

Tried the example for PLL in one of my experiments, guys let me know if it works or not. Enjoy

I updated my attachments with the experiment specs.

[Michael Arnold]

Here is the update of my example for the PLL with specs for the experiment, from my last post. Enjoy

[Michael Arnold]

Sorry guys my experiment circuit discription for VCO out was not correct, it was bassed on the free running internal frequency of 68.2khz, The internal free running frequency should be 25khz for the PLL to lock with 25Khz generator frequency. I Also included the non filter circuit in the example to show the difference in designs.

[Michael Arnold]

Updated the discription for the virtual pll zip circuit

[theriver1]

Can anyone tell me please how I could stop or block phase locked loop wireless signals ?

[s15t1]

can u please attach the zip file again , its showing corrupted,

[jotalo]

Can u send me the original Eule's identity Circuit, It seems to be damaged. Thanks

[Euler's_Identity]

I cannot believe this thread of over a decade ago still holds interest.  I'll see if I can dig it up -- there is much dust on it.

[3d0g]

That's truly amazing.  A Multisim circuit dropped in here over a decade ago still runs just fine.  I had to fire it up, again, just for the nostalgia of it.  Simplicity.