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Diligent boards with Vivado in multisim

I am an instructor using the diligent basys 3 board for teaching an introductory class on digital logic and PLDs.

 

I am using the student version of multisim and Xylinx Vivado 2015.4 64bit.  I am trying to use the schematic entry found in Multisim's PLD design module.  I enter everything and then select Transfer>Export to PLD>Generate and Save PLD file option.....  I then hit "finish" and I get the following error message:

 

Multisim  -  Monday, August 1, 2016, 5:20:03 PM
 
PLD topology check [Programmable Logic Device 1]  - Monday, August 1, 2016, 5:20:03 PM
Completed;  0 error(s), 0 warning(s), 0 filtered error(s);  Time: 0:00.01
 
PLD Export [Programmable Logic Device 1]  - Monday, August 1, 2016, 5:20:46 PM
Selected tool: Xilinx Vivado Design Suite 2015.4 64-bit
****** Vivado v2015.4 (64-bit)
  **** SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015
  **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
source {C:\Users\Owner\AppData\Local\Temp\NiCds\pld_export_1\vivF75F.tmp}
# create_project -force vivado_project c:/users/owner/appdata/local/temp/nicds/pld_export_1/vivado_project -part xc7a35tcpg236-1
# set_property target_language vhdl [current_project]
# set_property simulator_language vhdl [current_project]
# add_files -norecurse {c:/users/owner/appdata/local/temp/nicds/pld_export_1/pkg.vhd c:/users/owner/appdata/local/temp/nicds/pld_export_1/topvhdl.vhd}
# add_files -fileset constrs_1 -norecurse {{c:/program files (x86)/national instruments/circuit design suite 14.0/pldconfig/digilentbasys3.xdc}}
ERROR: [Vivado 12-385] Illegal file or directory name 'c:/program files (x86)/national instruments/circuit design suite 14.0/pldconfig/digilentbasys3.xdc'
INFO: [Common 17-206] Exiting Vivado at Mon Aug 01 17:20:51 2016...
Error: The current step failed. Export aborted.
Completed;  1 error(s), 0 warning(s);  Time: 0:05.23
 
The file diligentbasys3.xdc is in the directory path shown above... but for some reason multisim bombs out at this point.
I have tried this on a separate computer with the same installation and it bombs out on the same error.....
 
Any thoughts on this problem?
 
Thanks
TysonR
Message 1 of 6
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Hi Tyson,

 

Thank you for reaching out to us about this question, I have done a little research about the issue that you are describing here and found this Knowledge Base article that actually talks about this as a known issue for versions of Xylinx Vivado 2015.3 and later. 

 

In that same link you can find some workaround so that you can get the proper directory format to the file and work witht he software. 

 

Please let me know if you find that helpful or if you had any troubles with that it.

 

Regards,

Sil.VI
Message 2 of 6
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S.Jimenez-

Thank you for your help!  That got me a lot closer.... However, I still bombed on an error that gives me even less information... See the log below...

 

Multisim  -  Tuesday, August 2, 2016, 8:08:21 PM
 
PLD topology check [Programmable Logic Device 1]  - Tuesday, August 2, 2016, 8:08:21 PM
Completed;  0 error(s), 0 warning(s), 0 filtered error(s);  Time: 0:00.00
 
PLD Export [Programmable Logic Device 1]  - Tuesday, August 2, 2016, 8:10:09 PM
Selected tool: Xilinx Vivado Design Suite 2015.4 64-bit
****** Vivado v2015.4 (64-bit)
  **** SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015
  **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
source {C:\Users\Owner\AppData\Local\Temp\NiCds\pld_export_1\vivD598.tmp}
# create_project -force vivado_project c:/users/owner/appdata/local/temp/nicds/pld_export_1/vivado_project -part xc7a35tcpg236-1
# set_property target_language vhdl [current_project]
# set_property simulator_language vhdl [current_project]
# add_files -norecurse {c:/users/owner/appdata/local/temp/nicds/pld_export_1/pkg.vhd c:/users/owner/appdata/local/temp/nicds/pld_export_1/topvhdl.vhd}
# add_files -fileset constrs_1 -norecurse {c:/users/owner/desktop/digilentbasys3.xdc}
# update_compile_order -fileset sources_1
# update_compile_order -fileset sim_1
# launch_runs synth_1
[Tue Aug 02 20:10:36 2016] Launched synth_1...
Run output will be captured here: c:/users/owner/appdata/local/temp/nicds/pld_export_1/vivado_project/vivado_project.runs/synth_1/runme.log
launch_runs: Time (s): cpu = 00:00:01 ; elapsed = 00:00:10 . Memory (MB): peak = 199.805 ; gain = 11.535
# launch_runs impl_1 -to_step write_bitstream
[Tue Aug 02 20:10:36 2016] Launched synth_1...
Run output will be captured here: c:/users/owner/appdata/local/temp/nicds/pld_export_1/vivado_project/vivado_project.runs/synth_1/runme.log
[Tue Aug 02 20:10:36 2016] Launched impl_1...
Run output will be captured here: c:/users/owner/appdata/local/temp/nicds/pld_export_1/vivado_project/vivado_project.runs/impl_1/runme.log
# wait_on_run impl_1
[Tue Aug 02 20:10:36 2016] Waiting for impl_1 to finish...
[Tue Aug 02 20:10:41 2016] impl_1 finished
wait_on_run: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 205.746 ; gain = 0.000
INFO: [Common 17-206] Exiting Vivado at Tue Aug 02 20:10:41 2016...
Error: The current step failed. Export aborted.
Completed;  1 error(s), 0 warning(s);  Time: 0:32.84
 
It appeared to bomb out while exiting Vivado.  No .BIT file created.  Any other thoughts?
 
Thanks for all of the help so far!!
TysonR
 
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Message 3 of 6
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Hi Tyson!

I'm having this issue as well, were you able to figure this out?

Thanks in advance!

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Message 4 of 6
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TysonR,

Could you share how you solved this problem

I am having the exact problem and have tried all possible solutions I know but no success.

ERROR: THE CURRENT STEP FAILED: EXPORT ABORTED.

I would appreciate any help;)

 

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The problem I had was the location of the user constraint file named DiligentBasys3.xdc.  By default the directory path that Vivado uses is too long for Vivado to utilize.  So I had to move this file to the desktop and point the user constraint file location to the desktop location.  See my attached handout for a solution.

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