I am an instructor using the diligent basys 3 board for teaching an introductory class on digital logic and PLDs.
I am using the student version of multisim and Xylinx Vivado 2015.4 64bit. I am trying to use the schematic entry found in Multisim's PLD design module. I enter everything and then select Transfer>Export to PLD>Generate and Save PLD file option..... I then hit "finish" and I get the following error message:
Thank you for reaching out to us about this question, I have done a little research about the issue that you are describing here and found this Knowledge Base article that actually talks about this as a known issue for versions of Xylinx Vivado 2015.3 and later.
In that same link you can find some workaround so that you can get the proper directory format to the file and work witht he software.
Please let me know if you find that helpful or if you had any troubles with that it.
Thank you for your help! That got me a lot closer.... However, I still bombed on an error that gives me even less information... See the log below...
Could you share how you solved this problem
I am having the exact problem and have tried all possible solutions I know but no success.
ERROR: THE CURRENT STEP FAILED: EXPORT ABORTED.
I would appreciate any help;)
The problem I had was the location of the user constraint file named DiligentBasys3.xdc. By default the directory path that Vivado uses is too long for Vivado to utilize. So I had to move this file to the desktop and point the user constraint file location to the desktop location. See my attached handout for a solution.
Thanks very much for your efforts. However, it seems that it still can not successfully generate the BIT file. Is there any progress that you have made?