Multisim and Ultiboard

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D_CHIP - BAD BIT CHARACTER

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Hi everyone,

I think d_chip model is a very powerfull feature of multisim, but I have a lot of problems using it.

Last one is an error displayed when I start a simulation with a component using d_chip model :

 

multisim-error.PNG

Here is the code of the model :

.model MTest  d_chip(behaviour= "
+/inputs A0 A1 A2 A3
+/outputs D0 D1 D2 D3
+/module M
+/inputs I3 I2 I1 I0
+/outputs D3 D2 D1 D0
+/table 16
+LLLL LLLL
+LLLH LLLL
+LLHL LLLL
+LLHH LLLL
+LHLL LLLL
+LHLH LLLL
+LHHL LLLL
+LHHH LLLL
+HLLL LLLL
+HLLH LLLL
+HLHL LLLL
+HLHH LLLL
+HHLL LLLL
+HHLH LLLL
+HHHL LLLL
+HHHH LLLL
+/endmodule
+/instance M A3 A2 A1 A0 D3 D2 D1 D0
+")

The aim is to create a ROM component that students can easily edit with a webtool I have created. It will generate the code of the model. But, currently, I have this error message while I write the code manually on Multisim (v11). On the v14, no error is displayed, but the component does nothing.

I don't understand. So, if you have any idea, your help will be appreciated.

Thank you by advance.

 

PS : NI, It will be very helpfull to have more detailed errors from the d_chip parser.

 

Charles

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Solution
Accepted by topic author cmeunier
05-22-2019 11:07 PM

Hi,

Solved problem !

 

Using /table directly in the d_chip behaviour seems to work only for models with one output.

 

It seems when we use a d_chip model with several outputs, it is necessary to use /module to define the behaviour of each output.

 

In so doing, no more error and the component gives good outputs states.

 

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