Hello all!
I can make asynchronous J/K counters of any modulus, except one that starts at 3.
The attached file is set to start at 0000, but if you set it to start at 0011 (remove VCC from the PS terminal of U1A and U1B, and connect them to the NAND gate output, and tie the CLR on U1A and U1B to VCC), I'm given a convergence error. I've tried switching out components, and changing some simulation options, but I can't seem to get it to simulate.
Thanks for any help you can provide!
