Conflict behavior of DEC_BCD_10_INV between Multisim simulation and demonstration on Basys 3 board.

[waldenlian]

Recently, I use the DEC_BCD_10_INV component in Multisim to serve as a decoder in my circuit design. When I simulate the circuit in Multisim, the behaviors are as expected. However, when I export the PLD design into the Basys 3 FPGA board, strange things happen. The decoder does not work as expected. Instead, it works as follows:

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4-bit binary number  The port which is in high voltage

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0000                         O0

0001                         O3

0010                         O4

0011                         O5

0100                         O2

0101                         O1

0110                          O8

0111                          O7

1000                         O6

1001                         O9

Then I find that the problem may lie in the pin assignment of this decoder since the attribute of this component shows following information. The order of O0~O9 corresponds to the above strange results. However, I still don't know the exact reason behind it. Is there any reasonable interpretation regarding to this decoder?