Multisim and Ultiboard

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Blind Vias in Ultiboard v9 and v10

I have been dealing with EWB for some months now on a problem with placing blind vias into Ultiboard designs.  They have been "working on it" without any good solutions.  I would like to see if there are other users with this issue.  For grins I would like users to set up a 4 layer PCB in the PCB Options.  Check that the blind vias checkboxes are checked.  Draw a board outline and then place a via inside the board outline.  When prompted set the via to go from Copper Top to Inner1.  Next check the 3D view.  Note that the via at this point is blind and does not appear on the Copper Bottom.  Now right click on the via in the design window and select Properties.  Now click on the Autorouting Layers tab.  Note that the only checkboxes that appear are the Copper Top and Inner 1.  Click OK.  Right click the via again and select Properites.  Once again check the Autorouting Layers tab and notice that all the layers show up (Copper Top, Inner1, Inner2, and Copper Bottom).  Now check the 3d view and note that the via has magically became a through hole and shows up on the Copper Bottom.  The real gotcha is that if we hide the Copper Top and Inner1 in the design view the via will not show up on Inner 2 and Copper Bottom.  The other gotcha is that if we were to export the Gerber data we would find there is truly data on all 4 layers.  This is not an easy fix inside your design once this happens.  Even if you do the "work around" that EWB told me to do it still does not update the Excellon Drill output.  I had to manually tweak the drill file even after I went through the "work around" process.   I just want to verify that I am not alone in this anomoly.  I can't believe that it is something specific to my system and furthermore I can't believe that this has made it clear to version 10!  Don't get caught like me deep into a design with a number of blind vias and find out about this.  EWB you have a MAJOR problem.
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Hello bgoracke:

First of all - thank you very much for your feedback - we always welcome your comments to help drive continued improvements to the product platform. The problem that you are encountering with Ultiboard 9/10 has come to the attention of the Electronics Workbench Group R&D team very recently. Based on the importance of the issue, R&D has given it a very high priority. It is currently being fixed (and tested) and it will be available in the next update for version 10.

For anyone currently facing the same issue with blind or buried vias in Ultiboard, the workaround is to avoid loading the properties for that via. Simply place the via in the board and do not call its properties after placement. Currently, loading the properties (double-click or by right-click>properties) resets the via settings and causes it to become a via that crosses all layers. If you accidentally load the properties, click Cancel and it won't modify the via. Clicking OK or Apply will reset the via to a through-board via. If you have currently some vias with this issue, you can 'replace' them with new vias and the error will be eliminated.

Best regards,

  • Nestor Sanchez
  • Applications Engineering
  • Electronics Workbench Group
  • National Instruments
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