Hi, each flip-flop has a pair of asynchronous SET-RESET inputs. Asynchronous means that the circuit does not wait for a valid clock edge to trigger a change at the output. Thereby, activating (PRE)SET will bring you immediately to Q=1 and Qb=0 while activating RESET gives Q=1 and Qb=0. These inputs should typically not be activated simultaneously. Also, they can be active LOW, that is activated by a 0, or active HIGH, activated by a 1.
The Multisim Live JKFF model has active HIGH PRESET and RESET. In your state machie you usually don't want to have asynchronous signals since that can lead to unpredictable behavior. That's why I connected these to logic 0.
The starting state of a state machine depends on small voltage/current/impedance imbalances, inherently present in a real circuit. Initialization is also possible. In a simple circuit like yours you can connect an RC divider to your RESET pins. The resistor should be connected between RESET and GND while the capacitor between RESET and 5V. Initially your capacitor holds 0 charge and pulls RESET to 5V. Then it charges through the resistor and the RESET decays toward GND. Essentially this generates a short RESET pulse that brings all your FF-s to 0. When the pulse disappears, the RESET remains inactive during the normal operation of the circuit.
