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3 bit JK flip flop outputs

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  this is my first post here, I am hoping someone could offer some help to my knowledge gap.


I am designing a 3 bit Up/down counter for a university assignment but my component knowledge is lacking. This is my first ever module looking at circuit design so go easy on me 🙂


So I have created my K-map / boolean algenbra and connected the Q and Q(not) for all of my flip flops but now I have to connect the outputs to a 7-seg display to count up and down. This si where my knowledge is lacking as I cannot get the display to work correctly at all. 

I tried to connect up and 4511 BCD device with 4 inputs and 7 outputs. Well, the 7 seg display ahs 7 connections for the outputs but as for the BCD inputs, well there are 4. Now if I use all three JK's then I have 6 connections. I feel like I am missing something really simple here!


Hopefully I can get popped back onto the right path.


Best Regards

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Message 1 of 11

The 7-segment component inputs are binary encoded. This meas that you encode a decimal 0 with the 4 bits 0000. You have to create a corespondence table beween the binary code from your flip-flops and the 7 segments. Each segment in the display is an LED having an anode and a cathode terminal. To light up a segment the cathode must be grounded and the anode must be pulled to a logic HIGH voltage


Imagine that the segments are noted with letters like



|f          b| 


|              |

|e          c| 



Now, if you want to display a 0 you need to light up all segments except g. Then your first lines in the 7 segment decoder truth table will be


b3b2b1b0 | a b c d e  f g

   0000      | 1 1 1 1 1 1 0

   0001      | 0 1 1 0 0 0 0



You can continue and fill in this table with the simbols corresponding to each binary encoded number b3b2b1b0. You will need 4 bits, that is 4 flip- flops to encode digits higher than 7. Every segment, a to g is then a logic function that you can minimize/implement by using a Karnaugh map and the combinatorial logic of your choice, gates, multiplexers, etc.


The 7-segment display in Multisim Live has common anode that should be tied to logic HIGH and individual cathodes that must be pulled to logic low to light up a cell. This means that the functions a...g in the example table above will be negated bit by bit. This means that your decode logic should be active LOW. 

Hope this helps.



Message 2 of 11

Hi  gabor_csipkes

   Thanks for the super detailed reply. Sorry I haven't replied sooner myself.


My counter actually only needs to count a maximum of 8. 0-5 as condition = good, 6-7 condition = bad. This is why I only have 3 JK's, not 4.


I was just getting confused as to how I can get 4 inputs for the BCD, which feeds the 7 out into the 7 seg.


I will try to fully digest your information in the morning. I have a few hours study time planned in for the morning around home schooling my own two kids! Life is pretty crazy at the moment!


Thanks again for the help 🙂

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Message 3 of 11

I made a youtube video to show my progress and hopefully highlight the problems im facing today.


I changed over the BCD - 7-seg circuit. Now if I remove the SET-PRESET 5v to the 3rd flip flop, I can successfully count to 3 (woohoo), once I introduce the third J-K the count becomes kind of random. Trouble is, I cannot see where I have gone wrong.

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Message 4 of 11
Accepted by topic author Dazzlaa

Hi, I wrote out a solution to your counter problem, it is easier to explain something this way. Please see the attached file. There are quite a few things you need to chew yourself through.


Are you attending digital design lectures or just trying to learn something new? In any case, I would recommend to get a good book or lecture notes in introductory digital design...nothing high level, just the basics like Karnaugh maps, gates, multiplexers, decoders, flip-flops, state machines.


Have fun counting 🙂 .



Message 5 of 11

That is really great that you have taken the time to do that for me. 


I am distance learning actually. Its become difficult through the covid situation as contact to the tutors etc has become harder. Mixed with the added pressure at home has made studying tough!

I have done K-maps and used a truth table for the flip flops prior to making my circuit design.

I noticed on your one you used binary. I actually used grey code and also incorporated my input (Y or not Y [car enter, car leave]) into my K-map. Now I maybe think this was a bad move so for the next couple of hours I am going to start a fresh with new K-maps and circuit design based from a binary count and use the input conditions like you have shown.

Hopefully I will get a better output this time! 🙂


I'll report back my findings.

Best regards

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Message 6 of 11

Hi, there.

 Would you be able to explain the aggregate part of doing next states a little clearer for me?

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Message 7 of 11

Hi, imagine the transition where the present state is 000. Depending on the counting sense, at the first valid clock edge your state machine will either go to 001 (count up with S=1) or to 111 (count down with S=0, equivalent with notS=Sb=1).


If the states are encoded with Q2Q1Q0, let's look at the 2 possible next states and analyze them bit by bit.

- in the next state the first bit, Q2+, either becomes 0 (when S=1) or 1 (when S=0). Notice the corelation between Q2+ and S.

      S=1 <--> Q2+=0

      S=0 <--> Q2+=1   --> on aggregate Q2+=Sb

- similarly, the second bit, Q1+ either becomes 0 (when S=1) or 1 (when S=0). Again

      S=1 <--> Q1+=0

      S=0 <--> Q1+=1   --> on aggregate Q1+=Sb

- the third bit, Q0+ becomes 1 regardless of S, so for both possibilities Q0+=1


Therefore, the aggregate next state will be Q2+Q1+Q0+=SbSb1. Your state machine takes a simple binary decision depending on the value of S. You can apply this logic to find the aggergate transitions for each present state. Since you mentioned Gary encoding, it doesn't really matter whether the states use binary, Gray or other encoding schemes. 


Hope this is clearer now.


PS. For quicker judgement, when you understand how the binary decision works, you can always answer the question: "What value of the decision parameters S leads to a 1 bit in the next state?" That value of S will be Q+. In the above example notice that for Q2 and Q1 it is Sb that leads to a 1 in the next state, so Q2+=Sb and Q1+=Sb.

Message 8 of 11

That is brilliantly explained, I get that method totally now! Had a brief chat with my tutor today also, he confirmed that for my particular application, grey code is not to be used due to its irregular count. This also explains my irregular count on my circuit! 


Right,... I have lots to do! Now armed with a better understanding of my task and how to tackle it. Thanks so much for the help 🙂

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Message 9 of 11


  I can happily report that after much trial and error, I finally have a working up down counter! (Yey!)


I have used the input signal to also trigger the clock of the circuit, this acts as a counter as things are entering or exiting the car park. 

However, a couple of things concern me and I hope you could help out again?

Firstly, on your circuit diagram, you used a logic low for the set and preset  pins of the JK FF. If I do this, then no functionality is present and no counting takes place. If I connect link all Set/Preset to a VCC +5V then the counting all works?


Also, my counter starts at a value of 7, not zero. I am thinking the Set/Preset issue maybe linked to this. I have read up on the functions of these pins but as a novice I am struggling to piece it all together.


Best Regards

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Message 10 of 11