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Multisim and Ultiboard Idea Exchange

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I'd like to have an option for automatically exporting simulation results to a selected file format, including automated resampling to a desired sampling rate. This is related to this previous idea. Preferably Multisim would also automatically discard the exported results from the memory.

I'd like to be able to set a large number of simulations to run, possibly including a wide range of parameter combinations through the parameter sweep analysis, and have the simulations run and be automatically exported to a selected output format without user interference.

Due to the memory handling issue I mentioned in the post linked above, I can currently only run simulations one by one manually saving the results in between. With an automated export I could leave the computer to run the desired combinations during nighttime and have it discard the exported results from memory, allowing the next set of simulations to run.

The Idea: It would be nice to be able to set a desired sampling rate for a transient simulation before starting the simulation.

Background: We need to run longish transient simulations with a reasonably small TMAX. But we don't need all the intermediate time points used solely for helping the integration to converge. Multisim claims to run out of memory after occupying somewhere around 1 GB of memory, sometimes less. This is not a OS or hardware limit, but something intrinsic to Multisim's memory handling. This behavior is more bug-like than a real limitation of the software.

The capability for resampling/interpolating is already available through the export to .lvm files (see attached figure). Although I think the memory handling issue should be solved separately, allowing Multisim to discard irrelevant time-points on the fly would spare precious memory during more demanding simulations.

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3. Schematic: To add active probe (see CircuitMaker 2000 solution).

With the 14 version release there are probes feature added that I did not have a chance to evalute however probe can be moved dynamically to the specific net to check a signal level (voltage or current) or when you place on a component so power dissipation can be measured and showed (power dissipation vs time).

Notes:

This idea is splitted from topic "NI Multisim - new ideas" posted in 2014:

http://forums.ni.com/t5/Multisim-and-Ultiboard-Idea/NI-Multisim-new-ideas/idi-p/2792686

If some ideas are implemented in NI Circuit Design Suite 14 they shall be skipped and topic can be removed by admin.

11. Simulation: To add component stress analysis but more advanced. The goal is to check maximum dissipated power according to derating power characteristics for resistors according to current operating temperature (TEMP parameter for circuit simulation) and maximum voltage for a components (resistors, capacitors).

Notes:

This idea is splitted from topic "NI Multisim - new ideas" posted in 2014:

http://forums.ni.com/t5/Multisim-and-Ultiboard-Idea/NI-Multisim-new-ideas/idi-p/2792686

If some ideas are implemented in NI Circuit Design Suite 14 they shall be skipped and topic can be removed by admin.

10. Simulation: To add additional drift tolerance (aging, humidity etc.) option for a components (resistors and capacitors). Please create an option to turn ON and turn OFF additional drifts globally for a whole circuit design and for specific component.

Notes:

This idea is splitted from topic "NI Multisim - new ideas" posted in 2014:

http://forums.ni.com/t5/Multisim-and-Ultiboard-Idea/NI-Multisim-new-ideas/idi-p/2792686

If some ideas are implemented in NI Circuit Design Suite 14 they shall be skipped and topic can be removed by admin.

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Multisim and Ultiboard Idea Exchange

Visible solder mask in 3D view

Temperature simulation

Automatic exporting of analysis results and discarding of exported results.

Multisim: option for setting a desired sampling before running the analysis.

Schematic: Add Darlingon transitors support

Digital Logic in Multisim Live

5. Schematic: To set some min and max limits for a voltage, current or power (they shall be visible in Grapher when you generate the plot).

4. Schematic: To add operating state annotation for transistors (active, cutt-off, saturated).

3. Schematic: To add active probe (see CircuitMaker 2000 solution).

2. Schematic: To add power bias annotation for a components.

1. Schematic: To make an option to lock REFDES during copying circuit to the new sheet.

18. Model: To add a module that can build a component model from characteristics from datasheet (eg. to track output voltage characteristics of voltage regulator and to build behavioral model).

17. Simulation: To add Worst Case option to Monte Carlo analysis to check ONLY endpoints values.

15. Interface: Batched analysis is fine, but it would be a good to see TEMP parameter visible in main window.

14. Grapher: To add 3D plots (see circuit optimizer).

13. Grapher: To add option to generate one report for Worst Case EVA, RSS and Monte Carlo.

12. Grapher: To add histogram plots for a Monte Carlo simulation incl. table with data: MEAN, SIGMA, UCL, LCL.

11. Simulation: To add advanced component stress analysis.

10. Simulation: To add additional drift tolerance (aging, humidity etc.) option for a components (resistors and capacitors) with an option to turn ON and turn OFF additional drifts globally for a whole circuit design and for specific component.

9. Simulation: To add assymetrical tolerances option for a components (resistors, capacitors, voltage and current sources etc.)