Hi Filipe,
thank you for your answer!
I figured out how I can gate my siganl with a digital gate! I'm using a TTL-Signal on PFI0 which is high for 10 microseconds. During this time I have two valid Signals on two analog channels (ACH0 and ACH1). So far I can aquire the Signal on ACH0 correct, but for the Signal on ACH1 the board is to slow to get the Siganl right.
So far I'm using the "Clock Config.VI" with a sample rate of 200k per second. I tried 400k and more, also, and signal improves but it is far from good.
Well, I don't think this is good for the DAQ-Board, because it is not made for this sample rate.
What do you mean with filtering the input with the array?
I'm using a multithreadtred programm on a dual-pentium III 550MHz machine! But if I
try to compare every value of the TTL-Signal (if I aquire it on analog channel) if it is higher than a given value, then LabView slows down and my buffer overruns and overwrites values.
Is there a better method than using "greater as" function with case-knote ?
Thank you for your reply in advance!
Stephan