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Timing specs for synchronizing multiple M series devices using PLL

Folks - We are considering swtiching from E series (4472) to M series (6289) PXI devices for a high channel-count acquisition project.

I've seen that the on-board clocks of M series devices can be phase locked to the 10MHz backplane clock using a PLL circuit. I've been looking for hardware specs to answer these two questions:

1) How accurate is the PLL circuit? Ie how much timing jitter should I expect between devices once they are "synchronized" in this way.
2) Given that the M series devices share a D/A converter, how evenly spaced are the D/A conversions across the channels on one device during one sample period? (I am continuously ampling many channels at the same time).

Thanks for any pointers to the relevent literature. I've checked the specs of the 6289 and the PXI chassis and haven't found anything that addresses this.


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Hi Cas,

The 4472 is actually a DSA board, not an E series card. To answer your first question: the PLL circuit is as accurate as the 10 MHz clock in the backplane of the PXI Chassis.

It looks like you are looking for the convert clock specifications in your second question. I found a few knowledgebases and example programs with more information about that. Please take a look at these and let me know if you still have any questions.

How is the Convert (Channel) Clock Rate Determined in NI-DAQmx and Traditional NI-DAQ?

Advanced Data Acquisition Series - Synchronization with NI LabVIEW and NI-DAQmx

What Is a Phase-Locked Loop (PLL)?

Convert Clock and Interchannel Delay with NI-DAQmx



Hal L.

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