Synchronizing multiple 7851/52R's

[Iron_Bars]

Hi,

What is the simplest way to synchronize multiple 7851/52R FPGAs on a 1062Q chassis? I see CLK10 and several trigger lines TRIG0-7. My application is pretty simple, I would like data acquisition to start simultaneously on analog input AI0 on each card. It would suffice for synchronization skew to  < 200 ns.

Is it just a matter of setting TRG0 high with FPGA#1 and reading it on FPGA#2? I presume that there is no buffering of the trigger in an 8 slot chassis. What is the difference between using CLK10 and the trigger lines for synchronization? Which is preferred?

Any advice would be appreciated.

[Terry_ALE]

https://www.ni.com/en-us/innovations/white-papers/10/timing-and-synchronization-in-ni-labview.html is broad but a good place to start. 

[Tepig · Accepted solution]

I think this question is not related to time synchronization.

We should focus on "How to make two devices synchronized with PXI trigger line".

It's not difficult, pretty easy. Each FPGA device has I/O node named "PXI_TrigX" and you can use the node.

For example...

<FPGA1>

Export clock signal to PXI_Trig0

<FPGA2>

Read PXI_Trig0 state in While or SCTL loop

As positive side using PXI_Trig line is that you can generate various clock signal.

When you adopt Clk10/100, the signal has fixed parameter, Duty = 50%, frequency = 10/100MHz.

[Iron_Bars]

Hi,

If anybody is interested I've attached pictures of the test VIs used to confirm synchronization better than 1ns (with 40 MHz FPGA clock). There are probably better ways to generate trigger pulses, but I prefer using counters. The manual recommends two ticks for guaranteed synchronization. Is my result trustworthy?