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Simultaneous analog input and digital output (with NI6221M). Critical timing.

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Hello!

 

Please excuse my bad english.

 

Idea:

I am developing a device for measuring absorbance of light in a test sample. The device will have 20 light emitting diodes (LEDs) and 30 light sensitive photodiodes (PD). I have a NI6221M PCI board. As there are a lot of LEDs and PDs the device must utilize external multiplexing (MUX). The setup is shown in figure "DOAI System.JPG". The "delta t" shown in the figure is not important. It may be zero or a few us. That is not critical to the operation of the device.


Opreation:

PD 1 will be MUXed to the AI and the LEDs blinked (turned on and off), one at a time. Next, PD 2 will be MUXed to the AI and again all LEDs will be blinked one at a time. The sequence continues with PD 3, PD 4 and so on. Every blink of a LED should produce one AI sample. The sample rate of the AI must be about 12kHz (thus 80us per sample).

Q: Will this be possible to achieve with the NI6221M board?

 

Problem:

I realize that there will be problems. When the DO outputs an adress to the MUXs there will be a delay until the LED driver, PD electronics and the AI input amplifier have settled. Q: Is there a way to delay the AI sample clock some 10 microseconds as to allow this to happen? (Maybe to use an internal counter running at a much faster timebase than the 12kHz sampling or to use some other for me yet not known feature. Maybe to actually let the AI sample clock be the "master" and instead delay the DO clock.) Please see "AI timing.JPG".
Q: Is it possible to control the settle time for the AI? I.e. to tell the 6221 that it may use, say, 30 us to settle before it reads the value. Will those 30 us happen before or after the sample clock flank?

 

Any advice is much appreciated,

Markus

 

 

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We have decided to continue working with the ni6221 board. The delay problem was solved by using an internal counter that has adjustable duty cycle. The digital output is clocked on rising edge whereas the analog output is clocked on the falling edge. The duty cycle sets the amount of delay between the DO and the AI, allowing the optoelectronics to settle.

 

As the 6221 only has 8 clocked DIO lines we have added two multiplexers to allow 24 photodetectors.

 

However, we are not sure about the timing of the AI sampling. How can we be sure the AI sampling is completed before next DO is clocked? Is there a way to set the conversion time or to monitor when the AI sampling is complete? As for now, it seems to be working but we are not sure why...
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Solution
Accepted by topic author MarkusLindkvist

Hi!

Just thought I should complete this thread by posting the code we use now. The timing is as before but we added some property nodes to checka few parameters. Besides, the 6221 was replaced with a 6259Usb device that allows us to have better galvanic isolation and more synchronised digital IO lines.timing2.JPG 

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Hi Markus,

I'm doing something similar, but I encountered some timing problems. Could you post the whole VI, so I can see how it works and how you implemented the all tasks?

 

Thanks in advance

Gianluca

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Hi Gianluca,

 

I'm not sure I am allowed to post the complete VI since it might be protected by copyright law or things like that. I guess the company I'm working for owns it.

 

I made a print screen on the part that involves timing. Does that help?

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Thank you very much, it is very helpful. I have just a couple of question.

 

What is the name of this block (see attached image)? where is located in the function palette?

 

My main problem is to use one counter channel on my DAQ to generate a pulse train and contemporarily to act as a clock for measure (I want to pulse at 1 MHz and measure at 1 MHz).

 

Still thank you,

Gianluca

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It is called "Get terminal name..."

 

This link may help you finding it:

http://digital.ni.com/public.nsf/allkb/9D58153D1B5E5B66862574C8006A30FB

 

Cheers

Markus

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