PXI & cDAQ in a single TDMS

[Carisa_L]

Hi,

Yes, these devices cannot use an external CLK (what we call a Sample Clock) but need a master timebase. Unfortunately, the VI with the Counter task will not work unless you specify a counter rate of 1000S/s*31*256 = 7.936 MHz. The problem with this is that you cannot get this rate you need due to how the counter output is created. More detailed information can be found in this KB: http://digital.ni.com/public.nsf/allkb/68CF53DEBD970A6C8625795F005BC6BE?OpenDocument

You can use channel expansion and decimation (resampling down) to get to 1kS/s. The 9237 supports a 2kS/s sample rate which can then be decimated to 1kS/s. 

Regarding the 5 tasks and 4 TDMS streams, it would probably be best to use option b but you can try using option a and concatenating all of the waveforms into one TDMS file. You may run into memory issues using only one loop without using producer/consumer architecture, but it depends on how long you plan to run your system. 

Thanks,

Carisa

[golubovski]

Carisa & Sean,

Thank you both!

1. Sync issue

I will use 2048 S/s and ownsample to 1024 S/s on all 4 chassis. START of all 4 DAQ tasks will be the only synchronization between the 4 chassis on the respective PFI0 pins. ChannelExpansion will be used for all 4 DAQ tasks within each chassis. This should be OK with respect to the jitter considering the short DAQ duration (10min max)?

2. MultiDAQ loop & TDMS

I will use a producer-consumer loops like in my current setup. In the producer loop I will put all 4 "DAQmx Read.VI"s. In the consumer loop I will stream to 4 TDMS files. Now my question is regarding the data packing for the FIFO - Will all 4 data chunks arrive more or less simultaneously (1 from MXI4 and 3 from TCP) to allow me pack all 4 chunks for storing into the single FIFO or do I have to use 4 separate FIFOs?

Thanks in advance,

[Carisa_L]

Hi,

1. Be careful of coercion with that sampling rate as per the linked KB in the previous post. Otherwise, it should be okay.

2. I would recommend using 4 separate FIFOs.

Best of luck with your application,

Carisa

[golubovski]

Hello again Carisa,

1. I have tested the PXI-4472, it can sample both "decimal" and "binary" Fs, so it was successful with exactly 2048 which would work with NI-9237.

2. Using separete FIFOs would imply race conditions inside the producer loop, so it becomes natural for me to use 4 producer loops and 4 consumer connected with corresponding queues.. - would this be correct or should I stick to a single producer loop and 4 (?) conusmer loops? If first is orrect (4 producer loops) how to perform simultaneous STOP since only the PXI loop can sense the DAQ is over, via the DI task. Since all 4 loops would be asynchronous, I would like them to make identical number of iterations with identical chunks od samples-per-channels. What is the most efficient way to perform that synchronous STOP on the 3 cDAQ loops?

I still have not got the cDAQ equipment - does it make sense to test throuput issues with simulated cDAQ-9188s, or do I have to wait for the real stuff?

Regards,

[Carisa_L]

Hi,

I apologize for misunderstanding your question regarding the 4 FIFOs. I assumed we were talking the about the DAQmx reads. Once you concatenate your data you would only need one TDMS FIFO. 

I think it would be best to test the throughput with the read hardware.

Best,

Carisa

[golubovski]

Sorry for the missunderstanding Carisa,

You were right - I was talking about the pre-concatenating situation. Should I use 4 producer loops for the "DAQmx REad.VI"s or a single can handle them all. And if 4, how to synchronize their STOP having in mind I need them to read same amount of samples...?

Can you please analize my previous post in this sense?

Thanks in advance,

[Carisa_L]

Hi,

No worries. A single loop should be able to handle the 4 DAQmx Read VIs.

Best,

Carisa

[golubovski]

Carisa,

I have attached DAQ.PNG according to our discussion.Can you confirm this is what you hava esuggested?

Explanation:

All 4 DAQ Tasks are configured in a VI that parses channel info from a configuration file. This VI configures Voltage and ACC channels (on individual channel level) for the PXI task and 3 SG tasks for the respective cDAQ-9188 chassis (#1 and #2 being full with 8x NI-9237, #3 having only 4x NI-9237). In DAQ.VI I wiring is self-explained. I use parallel error flows to allow asynchronous iteration completion of all 4 DAQmx_Read.VIs in the producer loop, and of the all 4 TDMS_Writes.

Questions:

1. Is DAQ.VI correct or needs modifications? All START triggers come on PFI0 pins (/PXI1Slot2/PFI0, /cDAQx/PFI0)

2. Is task configuration OK with channel-by-channel method (ACC and SG PNGs) for both PXI-4472 and NI-9237?

3. Can NI-9237 sample with exactly 2000 S/s (because I get this from the 12.8MHz timebase with divisor N=25)?

4. We will use HALF bridges with an active and passive SG (latter for temperature compensation):

    (a) is Half Bridge Type I the correct configuration or have I defined a QUQARTER bridge?

    (b) can I shortcut the RS and EX points for remote sensing, or need I go with wires from RS to the bridge points?

5. Will MAX remember which cDAQ chassis is which (#1, #2, #3) or do I have to watch for this?

I guess Sean can help with some of my questions I have to ask because the equipment comes to customs just a day before the customer.

Thank you in advance,