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PXI & cDAQ in a single TDMS

Hello,

 

I have a situation I have to explain before I ask my questions. We have scheduled an experiment for 5 May and the procurement procedure for the hardware (NI acquisition, PCB accelerometers, strain-gauges, etc.) is still not even started. Therefore I have to cinsider the setup functionality of the current and anticipated new DAQ in advance since I won't be able to develop it when it comes.

 

Currrent DAQ is a PXI consisted of PXI-1006 chassis, 9x PXI-4472 and a 1x PXI-6713. Attached is the diagram of the DAQ VI. It acquires 72 channels (ChannelExpansion synchronized) and streams to disk (TDMS) and TCP (NET). An embedded controller makes a relay's contacts while producing controlled exscitation of our shaking table. So, The DAQ is triggered for START with the rising edge of this TTL pulse sensed off the DSA in slot 2. A digital line DI0 waits for the pulse to end (become low level) to STOP the DAQ. Within the ChannelEpansion ST master broadcasts its timebase to the rest of the DSAs.

 

We will order the following cDAQ system - either 3x cDAQ-9188 with 20x NI-9237, or 2x cDAQ-9188 with 16x NI-9235 (lets asume the later - 128 quarter-bridge 120 Ohm channels). My questions reflect my desire to synhronize both the PXI and the cDAQ systems (START and CLOCK) and integrate all 200 channels into a single TDMS file! SO far I could only simulte the [cDAQ] since neither I have access to that hardware, nor "my" applications engineers to be able to test my ideas (proposed diagram solutions). I would appreciate if somebody from NI App Eng Support could answer/test the following 2 scenarios:

 

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(A) ChannelExpansion solution

I have configured simulated [cDAQ] configuration of 2x cDAQ-9188 equipped with 16x NI-9235. On my surprise, LV allowd me to combine my complete [PXI] and [cDAQ] into a single ChannelExpansion. AFAIK, that means that NI-DAQmx knows how to share and route START Trigger and CLOCK from the ST master within the [PXI] to the [cDAQ] consuisted of 2 chassis! If this is TRUE and working, than I have no problem and I just have to know the requirements of this ChannelExpansion - which PFI pin of both chassis to inmort the START trigger from WHICH SOURCE and which to import the CLOCK divided from the PXI-4472 TimeBase AND I GUESS ROUTED VIA A COUNTER AND DIGITAL OUTPUT FROM THE PXI-6713 which would be the only possible way!?

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(B) Synchronized [PXI] and [cDAQ]

I need sampling to be 1.000 S/s (the minimum of PXI-4472). NI-9235 can only go down to 1.6 kS/s but can import external CLOCK lower than 1 kS/s. I need to START simultaneously my [PXI] and [cDAQ] and if possible share CLOCK for [cDAQ] divided down from the [PXI] ST master. Here are my options:

 

B1. START Trigger

I can pass the same RISING-EDGE of the TTL pulse to the PFI0 pins of both cDAQ-9188 chassis and route it on their NI-9235 modules via the "Timing.VI".

 

B2. CLOCK Sync

Ideally I would like the PXI-6713 to divide down ST TimeBase to 1kHz and pass it through (I guess) a CTR followed by a DO line, and exported to the other PFI pins of both chassis.

 

B2. CLOCK Source

If B1 is not possible, than I would like to use the PXI-6713 CTR to generate 1kHz TTL signal to export it via a DO to the PFI pins.

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Could this be tested by NI App Engineer?

 

Thanks in advance,

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I am attaching the VI I use when I generate the excitation instead of the embedded controller via the PXI-6713. I just tell the PXI-6713 to listen to the ST TimeBase - obviously NI-DAQmx implicitly divides down its Update CLOCK from the StarTrigger. How can this CLOCK be exported from here to a DO line?

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Hi golubovski,

 

It is not possible to synchronize PXI and cDAQ. While they can share the start trigger, they cannot share the clock. The reason for this is because the maximum frequency for the cDAQ chassis PFI lines is 1MHz and the 9237 modules require at least ~3 MHz. I hope this helps answer your question on a system level. Have a great day!

 

Best,

Carisa

Applications Engineer
National Instruments
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Carisa,

 

I would like to EXPORT 1kHz CLK from PXI-6713 to the PFI1 inputs of both cDAQ-9188 and route it as external clock to the NI-9237s as they can work on this CLK if it is external. With the 2nd VI diagram (with AO signal generation) where PXI-6713 generates AO with UpdateRate of 1000 S/s I have my desired CLK "inside" the PXI-6713 (divided down from the ST timebase) - how can I route this 1kHz CLK to a DO line or CTR-Output line to pass it on to NI-9237s via their chassis' PFI1 inputs?

 

Thanks for responding,

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In addition to the "exporting clock" issue, I am attaching a VI with integrated CLK from CTR1. Both work separatly - the AI and DI work as in the original PNG above (1st post), and the CLK generation works separatly also. Now how to START Trigger them synchronously? The DAQ is triggered externally via the TRIG input of the ST master DSA [/PXI1Slot2/PFI0].

 

Question is - do I need another wire to connect the same source to the CTR1-Gate and expect the StartTrigger from [/PXI1Slot11/PFI4], or is there a way to route the StartTrigger for the AI received at [/PXI1Slot2/PFI0] from DSA at PXI1Slot2 to the MIO at PXI1Slot11?

 

Thanks in advance,

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Hi,

 

It is true that the 9237 can accept an external clock, but this clock must also be 3MHz (which is what we call the master timebase or oversample clock). So really, the only external clocks that you can use must come from another similar DSA module in the same chassis or must be created with a counter.

 

Alternatively, you could export the start trigger and sample clock from the 9237, but you won't be able to use it with another DSA module because they need an oversample clock. You could route it to the PXI system or other cDAQ chassis for use with non-DSA cards. 

 

Thanks,

Carisa

Applications Engineer
National Instruments
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Hi,

 

You can use the DAQmx export signal or DAQmx connect signal VIs to route your start trigger to the trigger bus. In your other task in slot 11 you can specify the start trigger to be located on the trigger bus. Since this sounds like a multi-segment chassis, you need to make sure that you route the trigger lines correctly between the segments in Measurement & Automation Explorer (MAX).

 

Thanks,

Carisa

Applications Engineer
National Instruments
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Carisa,

 

Thank you for being with me on this as I cannot test my ideas since the equipment will arrive the moment it needs to work! I have 2 options for the CLK issue and another concern regarding the overall data thtoruput. So I'd be grateful if you consider the following for a comment.

 

1. External CLOCK

Attached is a CTR task to generate 1kS/s CLK from a cDAQ-9188 counter to drive 8x NI-9237 in its slots. Is this generating 1000 S/s proper for a ChannelExpansion of 32 strain-gauge channels task? Missing is the START trigger on the PFI0 - can the same be applied to both the AI and the CTR tasks as I want the CTR to start generating CLK sychronously within the complete system.

 

If this wouldn't work than I will probably use 2048 S/s AI on both the [PXI] and the [cDAQ] and resample down to 1024 S/s.

 

2. TDMS throuput

On the Diagram.png from the initial post you can see I use producer-consumer loops to relief the HDD stream (TDMS) from the TCP stream also needing the time stamping. I will remove this TCP burden from this paricular application to focus on the TDMS only. The system is now the [PXI] as defined above and the [cDAQ] is consisted of 3x cDAQ-9188 chassis with the total of 20x NI-9237 (80 SG channels) where 1st and 2nd chassis are full and the 3rd is half full (4 slots). If the CLK concept above (1) works than I would havel a total of 8 tasks:

 

[PXI-AI] 72x AI task combining Accelerometer IEPE and Voltage channels

[PXI-DI]   1x DI task tracking level-change on the START trigger to STOP the producer DAQ loop

 

[cDAQ1-AI]     32x AI task (all SG, strain-gauges)

[cDAQ1-CTR]   1x CTR task to generate the external CLK for the AI task

 

[cDAQ2-AI]     32x AI task (all SG, strain-gauges)

[cDAQ2-CTR]   1x CTR task to generate the external CLK for the AI task

 

[cDAQ3-AI]     16x AI task (all SG, strain-gauges)

[cDAQ3-CTR]   1x CTR task to generate the external CLK for the AI task

 

I plan to start all 8 of them sychronously with the same START trigger on the [/PXI1Slot2/PFI0] (working) and on [cDAQ1/PFI0], [cDAQ2/PFI0], [cDAQ3/PFI0]. I plan to put all 8 tasks in the producer loop to make use of loop's STOP condition. This means that I will pack possibly 152 channels in a single TDMS file sampled at 1kS/s (or 1024 S/s).

 

Since 72 channels are coming via MXI4 and 80 are coming from ethernet, is there a bottleneck in this concept or is this to be workng OK?

Do I need the consumer loop or am I safe to stream to TDMS inside the producer loop?

 

I appreciate a competent comment on this since I cannot test it (not by simulation anyway).

Thanks in advance,

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golubovski-

 

I am the DSA go-to for Applications Engineering and I wanted to reiterate some of Carisa's points.

 

-While the 9237 can take an external clock, the rate must be AT LEAST 3 MHz. So if you use a counter to create a clock for the 9237s, it must be at least 3 MHz. Creating a 1 kS/s clock with the counter will NOT work for the 9237s. Really, the most common use case for importing an external master timebase is when the user wants to synchronize multiple 923X devices. Using channel expansion, each module will use on master timebase created by one of the modules.

 

-Really, the only way you can do synchronization with the cDAQ is if you share a Start Trigger with all of the devices in the system and use a common master timebase within each individual cDAQ chassis. This of course isn't true synchronization as each device isn't sharing a sample clock, but this is the best you can do with cDAQ due to the PFI line limitations.

 

I am not sure if Carisa addressed the bottleneck question, but I will go ahead and give you my input.

 

For the PXI devices streaming via MXI-4:

72 channels * 3 bytes/Sample * 1000 Samples/s = 216 kB/s < 78 MB/s bandwidth of sustained throughput of the MXI-4 copper connection

 

For the cDAQ 9188:

80 channels * 3 bytes/Sample * 1000 Sample/s = 240 kB/s. Standard ethernet has a bandwidth of 100 Mb/s = 12.5 MB/s, so this should not bottleneck either. Network streaming is a little trickier to know for sure as every as every switch, router, etc. introduces more overhead and my prioritize data. It seems that if you have a dedicated network for this data acquisition, you should see no bottleneck for the ethernet systems as well.

 

I hope the synchronization is clear with the cDAQ devices. You could avoid all of this by using bridge PXI cards instead and truly synchronize everything.

 

Please let us know if you have any other questions.

 

Thank you,

 

Sean                                                                                                              

 

 

Applications Engineering Specialist - Semiconductor Test
National Instruments
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Hi Sean,

 

Thank you for your support efforts again! I admit I cannot follow you in detail so please help me comprehend both topics:

 

1. External CLOCK for NI-9237

The manual says with external master timebase we can go down to 391 S/s. If I understand you well this can only be done by supplying 3MHz master timebase (divided by 256, and than with 31) - the external source cannot be a CLK but a master timebase only? So the VI with the CTR task I had attached will not work for me? Is there a way to produce this inside the cDAQ-9188 chassis? Assuming the answer is still NO, do I have only one choice - to use ChannelExpansion with lets say 2048 S/s which can be resampled down to 1024 S/s which is closest to the desired 1 kS/s?

 

2. DAQ and TDMS loop(s)

If the outcome of the above [1] issue is to only StartTrigger simultaneously all 4 chassis (PXI and 3x cDAQ-9188) and they all sample at 2048 S/s (ncluding the PXI) independently, than what is your suggestion regarding the the 5 tasks (PXI-72xAI task, PXI-1xDI task, cDAQ#1-32xAI, cDAQ#2-32xAI, cDAQ#3-16xAI) and the corresponding 4x TDMS streams:

 

(a) use them all inside a single loop

(b) use the 5 tasks in a single producer loop and the 4x TDMS streams in a single consumer loop (via FIFOs)

(c) another more effective combination?

 

I have to ask since the cDAQ equipment is still not paid for and would be on my desk too late.

 

Thanks again,

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