Multiple questions PXIe-4302 calibration.

[Walsh90]

Attached is a copy of the data set from a passing test with the current cal procedure for the PXIe-4302 via Calibration Executive. My team and I have a couple questions in regard to this.

Firstly standard operating procedure has us calibrate 20% data points. Instead of the 0V, +/-0.1V, and +/-9.5V data points we would like to see: 0V, +/-0.1V, +/-2V, +/-4V, +/-6V, +/-8V, +/-10V. Is a script update possible for this?

While producing we run our cards closer to 10V. Is there a reason this test only reaches 9.5V. Is there some kind of soft limit where we see a performance decrease?

During our calibration we are using a HP-3458A which is communicating via GPIB. Are these two CPUs "playing nice"? The calibration procedure has us verify input impedance however we were under the impression that while the 3458A was in talk/listen mode the program would take care of this. Do we have to manually set this or is Calibration Executive taking care of this for us?

Finally, as you can see from the data the readings are simply labeled "Reading" is this coming from my DMM or the card or some calculation? I was hoping you could guide me to a way to log both my DMM and the PC output so we could verify and compensate for I2R losses and the like in my test setup.

Thanks.

[herringbone]

I'm not too familiar with the PXIe-4302 procedure, but I think you could answer your question by taking a look at the TestStand sequence files.

Editing the procedure is generally frowned upon, but taking a look would answer some of your questions about limits and extra data points.