Does anyone know what's the shortest digital pulse that a 6321 card can reliably detect? The specs sheet states about 1MHz rate for digital I/O and voltage limits for high/low states (e.g. minimum 2.2V for a high state) but I can't find information about timing specs, specifically minimum pulse widths.
In my application I want to use a 300kHz TTL(-ish) signal as the timing source for the ADC (ai) sample clock. Since the maximum A/D rate is 250kS/s I'll have to use a divider of 2-3, which shouldn't be a problem. The 300kHz TTL signal consists of rectangular pulses with a 3V high level (0V low) and a 200ns width connected to PFI0 with 50Ohm termination. I can't get it to be detected at all (e.g. counter input -> frequency measurement and implicit sample clock). If I remove the 50Ohm, the rectangle turns into an ugly exponential pulse train (like a sawtooth) with higher amplitude and much larger pulse width, and now it's detected by the DAQ. Of course I'd prefer to use the proper rectangular pulse shape to minimize jitter, but what are the limitations here?
