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Increasing sampling rate with external clock

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Hi all,

 

I am having DAQ PXIe-6361 and PXIe-8360 controller in a PXIe-1071 express chasis. Maxium sampling rate of my 6361 is 2 MS/s. But i want to use my daq with higher sampling rate. After going through various posts I decided for two options to increase my sampling rate. One is to  connect a signal generator of 5 MHz to use as an external clock . Other is to use PXI chasis synchronization clock

 

my question is 

 

1) What is the limit to the frequecy which we can use as external clock to the DAQ ? Which parameter is limiting the ADC perfomance if we are using higher frequency clock signal ?

 

2) I also come to know an option called " timebase in  PXI Express chassis". can I use this option ? Anyone please give me a link to a good tutorial on  timebase in a single PXI Express chassis ?

 

3) PXIe-1071 chasis has 100 MHz differential clock. Is it possible to use this as clock signal to my 6361 DAQ  ?

 

Regards

Vaidhin.

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Hi Vaidhin,

 

Trying to sample significantly faster than the spec'ed 2 MHz will result in a hardware error (Error -200019: ADC conversion attempted before the prior conversion was complete).  Rates slightly higher than 2 MHz may be sustainable, but keep in mind many specs (e.g. settling error) are based off of the 2 MHz maximum sampling rate and so would not apply.  At rates a bit above 2 MHz, you will get the ADC conversion error, which means that the samples are coming in faster than they are able to be converted and transferred to the on-board FIFO.  5 MHz would almost certainly be too fast (although you are more than welcome to try it out for yourself).  There is no software limit to the rate, so you can try to set it as high as you want using the internal clock to see what you can actually sustain (keep in mind available internally generated rates are 100 MHz / N where N is an integer).

 

To enumerate answers to your specific questions:

 

1.  Based on the spec the guaranteed maximum rate is 2 MHz.  The conversion time of the ADC is the limiting factor.  You can (probably) go slightly higher than this but you will get Error -200019 if you go too fast.

 

2.  I'm not sure what option you are referring to, but see below.

 

3.  No, the 100 MHz differential clock may only be used as a reference clock for the 6361.  The meaning of reference clock is that the 6361 itself has a 100 MHz on-board oscillator which may be phase-aligned with the backplane clock through a PLL circuit.  The oscillator (aligned or not) is then divided down to produce the internal sample clock.  You can't use the oscillator directly as the sample clock (the card is not capable of sampling this quickly and the direct route is not available anyway).

 

 

Best Regards,

John Passiak
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Hi John,

 

Thank you for the Information. 

The timebase in PXI Express chassis I am talking about is from section "Synchronization General Concepts" fron this document http://www.ni.com/white-paper/11369/en

 

 

 

Let me describe my task, so that you may propose some solution.

I bought the NI DAQ, chasis and controller as described in my post. My task is to sample and process analog signal upto 1 MHz frequency. But after purchasing the hardware, I realized the effect of high frequency noise and thermal noise which may aliase with my main signal. So I thought of overclocking the DAQ.

 

My signal parameters. Voltage : -10/ +10 , frequency : upto 1Mhz, Could you suggest me a signal conditioning card ? I will try to tweak my parameter limits if no card available with my parameters specifications.

 

Regards

Vaidhin.

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Accepted by topic author Neo6

HI Vaidhin,

 

The article does mention the backplane clock as a possible means for synchronization, but this is accomplished by using it as a reference clock to phase-align the onboard oscillators of your DAQ devices which are then divided down to produce the sample clock.  You can't use the backplane clock nor the onboard timebase directly as the sample clock (for one thing, these signals are far too fast).

 

Measuring 1 MHz with a 2 MHz DAQ device might not give you what you are expecting.  You'll only get 2 points per period of your input--this is right at the limit to prevent aliasing of your signal and of course will not give you a good characterization of the shape of your signal.  You might be able to push the card slightly beyond 2 MHz but not significantly enough to make a huge difference.  You are correct that if you have noise at higher frequencies it could be aliased down into your signal.  Any noise above ~1.7 MHz will begin to be attenuated by limited bandwidth of the 6163 (there is a chart in the specifications showing the bandwidth).  If you have noise in between 1 MHz (your signal) and ~1.7 MHz, you might look into an external filter, but agian you are still sampling very slowly to be able to characterize the shape of the signal.

 

The next steps up (in terms of sample rate) would be as follows:

 

4 MHz:  PXIe-6124

10 MHz: PXI-6115

 

There are currently no products that use the same DAQmx driver which can sample beyond 10 MHz, but NI does also have a line of digitizers which can sample much faster.  If you are interested in sampling up to 100 MHz you might consider looking into the PXIe-5122--there are also faster digitizers available but these are probably unnecessary for your application.

 

 

Best Regards,

John Passiak
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Hi John,

 

Thank you very much for the reply. Very Informative.

 

regards

Vaidhin.

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Hi John,

 

My question may seems pretty basic to you. But Could please explain how to calculate that, any noise above ~1.7 MHz will begin to be attenuated by limited bandwidth of the 6361 ? From which parameter in the specifications sheet should we use to calculate this limit ?

 

Thanks

Vaidhin.

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Hi Vaidhin,

 

You can refer to the graph on page 2 for the typical bandwidth of the 6361 (1.7 MHz is the point where you will see 3 dB of attenuation):

 

2012-05-23_114040.png

 

 

Best Regards,

John Passiak
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Hi John,

 

I have problem to acquire samples in very short period of time. I’m trying to acquire measurements from 16 channels from ultrasonic transducers. Using the NI-USB 6218 the maximum sampling rate(Hz) for the mesurements is 250kS/16 = 15625 S/sec (maximum sampling rate for 16 channels). I’m using  start trigger from PIC which connected to PFI0 and reference trigger (Stop) connected to PFI1 and sample clock of 8MHz from PIC connected to PFI2. I’m still wondering which sample clock should I use: onboard clock or PFI2? So I decided to use sample clock from onboard clock. The time taken from the rising edge of start trigger to falling edge of reference trigger is 0.92ms. During the time (0.92ms) I would like to acquire 5 samples from each channel. At the front panel I set-up the parameters as follows:

 

Channel: Dev1/ai0:15

Minimum value: -10V

Maximum value: 10V

Timing parameters:

Samples per channel : 5

Rate (Hz): 7000

Trigger parameters:

Start trigger : PFI0 ;   Start edge: rising

Stop/reference trigger : PFI1 ; Start edge: falling

 

Pretrigger samples: 2

 

At the DAQmx Read node I select “Current read position”. But when I’m running the VI the error display (error message.jpeg).If I use the sample clock from PFI2 I also received an error message (error message2.jpeg). Does the error comes from the sampling rate? I'm really confused.Pls tell me what I’m doing wrong here?

 

Tq

arelone

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Message 8 of 9
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I'll first answer why you are receiving errors in each case:

 

When using a reference trigger, a circular buffer is configured that allows you to read back pre-trigger samples once the trigger has been received.  You may use a start trigger along with the reference trigger--the start trigger will start the acquisition of samples into the circular buffer.  The normal use-case for a reference trigger is to read relative to "First Pretrigger Sample" (this is the default) and the effect would be a finite acquisition with a desired number of pre-trigger and post-trigger samples.  By reading relative to "Current Read Position", you will be reading back the contents of the pre-trigger buffer as it is acquired.  If you can't read fast enough to keep up, you would get an error (-200279 as shown in Error Message.jpg).  For example, at your rate of 7 kHz, the loop would have to run 1400 times per second (once every ~700 us) to keep up.  If you wanted to read data continuously as it is acquired, you should read it in large enough segments so that your software can keep up with the acquisition (I usually read around 100 ms of data per loop as a general rule of thumb).

 

Error Message2.jpg shows error -200019.  This is a bit more straightforward, it just means that the external clock is too fast for the ADC.  The hardware is given a clock edge while it is still acquiring the previous sample and returns an error.  This isn't surprising given that your external clock is 8 MHz while the maximum sample rate (according to the spec) of the 6218 is only 250 kHz.  So you definitely cannot use the external 8 MHz clock as a direct sample clock for the analog input of the 6218.

 

 

I think the confusion comes from trying to make use of both triggers.  It sounds like you want a finite acquisition of 5 samples starting from when the start trigger goes high.  If this is true, you could eliminate the reference trigger entirely--the acquisition will stop once it has acquired the desired number of samples if it is configured as a finite acquisition.

 

 

Best Regards,

John Passiak
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