I would like to syncronize the continuous mode multi-channel analog input measurements in my PXI system, but I am confused about how to accomplish this using the C-Function Drivers for two different product families.
Here is a layout of my system.
PXI-1033 Chassis:
Slot 2: PXI-6652 TCXO Synch. Board
External 10MHz reference on PFI1 -> PLL -> PXI_CLK10 on backplane
DDS generates Sample Clock Timebase -> Rear Synch Clock (Full Rate) -> Synchronous Routing to PXI_STAR0 & PXI_STAR1
Software Trigger connected to PXI_TRIG0 for Starting Acquisition on all AI Channels
After acquisition is started, disconnect Software Trigger from PXI_TRIG0 & connect to PXI_TRIG1 for Stopping Acquisition
Slot 3: PXI-5105 High Speed Digitizer/Scope (using NI-Scope driver)
Set NISCOPE_ATTR_SAMP_CLK_TIMEBASE_src=NISCOPE_VAL_PXI_STAR (External Sample Clock from PXI_STAR)
Set NISCOPE_ATTR_SAMP_CLK_TIMEBASE_RATE to 6652 DDS Frequency
Set NISCOPE_ATTR_SAMP_CLK_TIMEBASE_DIV to correct divisor value to get desired sample rate (say 500 kHz)
Set internal timebase reference to NISCOPE_VAL_NO_SOURCE (only option when using external sample clock)
Setup Triggers: NISCOPE_ATTR_ACQ_ARM_SOURCE from NISCOPE_VAL_RTSI_0 (PXI_TRIG0) and
Digital Reference Trigger from NISCOPE_VAL_RTSI_1 (PXI_TRI1)
Request only 1 post-reference sample so that continuous acquisition stops immediately after reference trigger.
Slot 4: PXI-6133 S-Series Multifunction DAQ (using DAQmx driver)
DAQmxSetSampClkTimebaseSrc to PXI_Star for external sample timebase
DAQmxSetSampClkTimebaseRate to 6652 DDS Frequency
DAQmxSetSampClkTimebaseDiv to correct divisor value to get desired sample rate (say 500 kHz)
Set Sample Clock source to ai/SampleClock using DAQmxCfgSampClkTiming (this is the divided down SampleClockTimebase?)
Set Start Acquisition trigger to PXI_Trig0
DAQmx cannot use a reference trigger to stop a continuous acquisition, so I guess I'll use DAQmxStopTask
(or I thought about disconnecting the DDS sample clock timebase from PXI_STAR0/1 in the 6652 so
that the 5105 & 6133 stop synchronously)
I think that this will work, but I'm concerned about a few issues:
(1) How to syncronize the timebase dividers in each device so that the 5105 sample clock and the 6133 sample clock are in phase?
Should I use NI-TClk functions like niTClk_ConfigureForHomogeneousTriggers?
Or, should I manually configure a Sync pulse from the 6652 to each of the units using a 3rd software trigger on PXI_TRIG2
going to NISCOPE_ATTR_CLOCK_SYNC_PULSE_SOURCE and DAQmxSetSyncPulseSrc?
(2) The 5105 specs show that the External Timebase can be any frequency from 8 MHz to 65 MHz. At sample rates < 8MHz, this is the reason that I need to provide a faster timebase and divide it down to get the sample clock frequency. Will the internal sample clocking performance be the same across the entire range? Does it expect discrete 1MHz steps between timebase frequencies, like the Reference PLL?
(3) What are the minimum and maximum values for the external timebase frequency for the 6133? (Anything up to 20MHz?)
Thanks in advance for tackling this one.