06-22-2007 06:22 AM
06-27-2007 05:10 AM
06-27-2007 07:18 AM
06-27-2007 09:55 AM
06-27-2007 10:29 AM
06-27-2007 04:51 PM
Ok, gotcha, and I agree that it's reasonable to expect to be able to read the entire buffer. In the apps I'd done that only needed most recent data, my buffer was generally times bigger than the amount of data I requested, so I never encountered the quirk you found.
Just a few more fairly long-shot thoughts:
1. Ever toyed with the DAQmx property for "data transfer request condition"? This property controls how samples move between the board's own built-in hardware FIFO buffer and system RAM over the PCI bus. I'm wondering if this magic # of 32 missing samples somehow relates to that FIFO? Perhaps you'd get different behavior by trying different settings there?
If so, it would seem like an implementation issue (bug?) because any data stuck on the board should be *more* recent than what you can read from system RAM.
2. Did you ever try reading 2 half-buffers and then combining them? Maybe DAQmx is trying to do you a favor you don't need. Many instances where someone attempts to read an entire buffer in a continuous acquisition would be a bad idea because the task is trying to write data to a memory location that is locked out due to the in-progress Read. You've paused your acq to try to avoid this problem, but perhaps there's something deep down in DAQmx that leaves 32 samples of fail-safe cushion...
-Kevin P.
06-27-2007 05:33 PM
06-29-2007 11:28 AM
06-29-2007 04:14 PM