07-14-2022 10:51 AM
Hello,
I have a PXIe-7846: Doc says Maximum Sample Rate: 500 kS/s:
Does this means I cannot emulate a SPI peripheral running at a clock speed of 1 MHz?
What is the maximum SPI clock speed that I can expect to handle with this device?
I may need to take multiple samples per half period to get good enough edge detection resolution (e.g. 10 sample per period ==> 500 KS/s / 10 ==> only handle SPI clock speed up to 50 KHz ?) This is strangely low considering the FPGA can run at 80 MHz. Am I understanding this correctly ?
Solved! Go to Solution.
07-14-2022 12:38 PM
Regarding the IO your assumption seems correct.
Regarding the FPGA, it could in fact go faster than 80 MHz. I do not think there are FPGAs that go slower. The benefit of an FPGA clocking at a rate higher than IO is that sometimes the processing needs more cycles that the IO.
07-14-2022 07:02 PM
Hi. 500kS/s is referring to Analog Input.
1MS/s for analog output.
And 10MSps for DIO(at MIO connector) due to signal integrity.
And 80MSps for DIO at DIO connector.
So your intuition and logic are correct!
07-18-2022 06:22 PM
I was able to emulate a SPI Peripheral that communicated in full-duplex with a TotalPhase Aardvark Controller talking SPI at 4 MHz. I was able to to set the response data MISO with a latency of only 40 ns after detecting a falling edge on SCK.
Final thoughts:
I think my cable lengths are too long because my setup fails at 8 MHz. Maybe that for higher clock speeds the USB-7846 would have been better because it could have been embedded closer to the device under test and thus have shorted wires, or maybe a SBRIO but not sure about the performance.