Can I change the pulse width of the NI sample clock ?

[Lou_III]

Hello, we use the PCI 6220 and 6250 boards and regularly export the sample clock from one board to another using a PFI output line so all our collected data is synchronized perfectly.  We are trying to also use this same sample clock as a source for a non-ni device (yikes) that requires a longer sample clock pulse width.  It seems the NI sample clock has a pulse train of ~40 ns pulses.  Is there any way using Daqmx that I can change this width to be something larger ? 

Thanks in advance,

Lou III

[Beutlich]

Both devices have two counters, and you can configure them to have different pulse widths and different frequencies, and you can synchronize the counters with other systems on the board so that the variable 'clock' is locked to the sample clock on the board. Using the counter will allow you to have greater flexibility in controlling the type of clock you send while maintaining the synchronization.

[Lou_III]

Unfortunately I can not use the counter's on these boards as they are already spoken for reading encoder signals.  I need to change the width of the sample clock itself and not take up a counter to make up my own sample clock.

[Beutlich]

The sample clock on the devices are 50% high and 50% low. You can change the pulse width by changing the frequency of the sample clock, but you cannot setup the clock to perform a PWM natively.

[John_P1]

Actually, the internally-generated AI sample clock is NOT a 50% duty cycle.  It should always be the same pulse width as the width of a convert clock timebase pulse (as drawn in the M Series User Manual😞

       

So, using the default 20 MHz timebase should give you a ~25 ns pulse width (which is actually measured 37.5 ns when I use my internal counter due to quantization). 

If you're OK with using the 100 kHz timebase for your analog input task, you can get a 5 us sample clock pulse width without having to use any counters.  The downside is that you won't be able to hit as many sample rates (you are limited to 100 kHz / N instead of 20 MHz / N):

To get the 100 kHz Timebase to show up in the drop-down menu, you'll need to right-click on it and enable advanced terminals.

Best Regards,

[Lou_III]

Interesting....I see that in the Daqmx C  this function is actuallyetSampClk_Timebase_MasterTimebaseDiv which has allowable values of 1 and 200.  This is pretty much what we were looking for but as you correctly guessedd the 100kHz / N  resolution limitation is a bit of a deal killer.  I do thank you for your suggestion though.

Lou

[John_P1]

Hi Lou,

Are you using the Frequency Generator (see manual)?  It's essentially a limited counter output that can generate a small number of frequencies: {10 MHz, 100 kHz} / {1:16}.

The output of the frequency generator is a 50% duty cycle.  If I set my Frequency Generator to 5 MHz and use this for my convert clock timebase, the sample clock pulse width is 100 ns.  2.5 MHz gives a 200 ns sample clock pulse width, etc.  You can probably use the Frequency Generator to find an acceptable frequency that gives a wide enough pulse width as well as a high enough resolution for your clocks.  Of course, there is a compromise--slower timebases give a wider pulse width, but less resolution when generating your clocks.

Best Regards,

[JB]

Hi Lou,

Would an external IC be an acceptable solution ?

Best regards

[Lou_III]

John P:

I didn't even remember that the card has a Frequency Generator but again resoultion is the problem.  Good idea though.  If we were building a one-off product this would work.  We could collect faster than we need to and decimate down but I'd rather not have that overhead as sometimes we run close to the edge as it is.

JB:

We were already going down the road of building a small pulse extender card to plug into the 3rd party hardware.  Ultimately this solution is a little ugly but realistically with how dynamic the entire product is it is the only realistic solution.

Thanks to all the posters for your great ideas.  Really impressed with the forum.  For now I think we can close the thread, hopefully somebody else can use one of those other suggestions down the road.

Lou III

[John_P1]

Hi Lou III,

I just wanted to clarify, I was discussing using the Frequency Generator as the Convert Clock Timebase.  The hardware would divide this down to get the actual convert clock, so you wouldn't actually need to acquire faster than you needed.  By default, the Convert Clock Timebase is 20 MHz, so by lowering it you would simply reduce the number of available rates (from 20 MHz / N, to X / N, where N is an integer).

Best Regards,