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Buffered Finite Pulse Train Generation

I am trying to create a finite pulse train with programmable pulse widths
(pulse width modulated digital info). The period will be a constant but
the duty cycle could be one of two values. Timing is very critical. I have
a PCI-6602. Please let me know if this is possible and if so, how?!
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You can do what you describe with the 6602 through a feature known as
Frequency Shift Keying (FSK).

In a nutshell, you set up a pulse train by setting Pulse Spec 1 and Pulse
Spec 2 attributes to be the high-level and low-level times of your train's
period. You also set up Pulse Spec 3 and Pulse Spec 4 to be the high- and
low-level times of another train with a different duty cycle. Once you run the
counter, you change the level of the counter's gate to choose between the train
defined by Spec1/Spec2 or Spec3/Spec4. The pulse train will change on the fly
with every toggle of your gate.

If you have NI-DAQ 6.6, you should have an example of this feature.

Regards,
Rich Yavorsky
NI

Tom Haggerty wrote:

> I am trying to create a finite pulse train with progr
ammable pulse widths
> (pulse width modulated digital info). The period will be a constant but
> the duty cycle could be one of two values. Timing is very critical. I have
> a PCI-6602. Please let me know if this is possible and if so, how?!
0 Kudos
Message 2 of 2
(2,249 Views)