fpga vision assistant gives unweired code

[JeroenP]

Hello everyone

I'm working with the new vision toolkit for FPGA ( vision 2014) it has been great so far. But last week i encountered something strange. i was using the FPGA vision assistant to create some code but when i opened it up there were unweired and blocks. [attachemtn 1] I got the same miss weiring every time.

I'm wondering if any of you also encountered the same? If so I guess it will have to become a bug report.

the second attachment is what i used in the vision assistant.

-i buffer the original image (U32)

-threshold according to some R G and B values

-buffer the ( U8 ) image

-reload the original U32

-mask according to the stored U8 image

I would like to hear your experience on this

Greetings,

Jeroen

[ChristopheC]

Hi,

It's a known cosmetic issue that does not affect the functionality of the code generated. The code should still compile and work just fine. It is not broken.

In some specific cases, we need to combine those signals, and it was just much easier to always generate that extra AND and leave it unwired.

I filed CAR 509005 to address it in a further release.

Christophe

[ChristopheC]

Since the FPGA functionality is new, we would appreciate any feedback for improvement or specific functions that you might want to be implemented in future release.

Feel free to post any suggestions/feature request on the new Vision Idea Exchange:

http://forums.ni.com/t5/Vision-Idea-Exchange/idb-p/visionideas

Best regards,

Christophe