FPGA Interface C API - Cannot read DMA FIFO using NiFpga_ReadFifo - Timeout error

[ArtB83]

Hi All, 

I'm using CVI2015 Sp1 and FPGA Interface C API to interact with FPGA module PXIe-7962R. The goal is to transmit and receive data, between 2 predefined channels (one for TX other for RX), using RS485 communication standard that implemented in FPGA.

I followed the NI example about FIFO write/read and created 2 separate functions, 1 for writing data and another for reading.

When writing the data into the DMA fifo I run the following sequence:

NiFpga_WriteFifoU64 (*session, NiFpga_rs485_HostToTargetFifoU64_FIFOIN, fifo_Arr, txNOElements, TIMEOUT_MILISEC, NULL);

NiFpga_AcquireFifoWriteElementsU64 (*session, NiFpga_rs485_HostToTargetFifoU64_FIFOIN, &txElementsAcquired, txNOElements,
TIMEOUT_MILISEC, &stArrTxChannelState[chnNum-1].m_writeElements,
&remainingTxElementsInDMA);

NiFpga_ReleaseFifoElements(*session, NiFpga_rs485_HostToTargetFifoU64_FIFOIN, txNOElements);

The return status of each function is 0. I assume that "write" was performed successfully because the txElementsAcquired is same as tx Number of elements that required to write.

When reading the DMA FIFO I created the following sequence - 

NiFpga_ReadFifoU64(*session, NiFpga_rs485_TargetToHostFifoU64_FIFOOUT,
(uint64_t*)rxData, rxNOElements, TIMEOUT_MILISEC, &remainingDMA_RxElements);

NiFpga_AcquireFifoReadElementsU64 (*session, NiFpga_rs485_TargetToHostFifoU64_FIFOOUT,
&rxElements, rxNOElements, TIMEOUT_MILISEC, &stArrRxChannelState[chnNum-1].m_readElements, &remainingDMA_RxElements);

NiFpga_ReleaseFifoElements (*session, NiFpga_rs485_TargetToHostFifoU64_FIFOOUT,
stArrRxChannelState[chnNum-1].m_readElements);

But the return status of NiFpga_ReadFifoU64 is always -50400 - which is timeout. I'm reading the same quantity of elements as were written in a write sequence. After NiFpga_AcquireFifoReadElementsU64 the number of acquired elements is always 0, and remaining elements in DMA is 2. 

When running the LV bitfile using LabView interface, the procedure works fine - so I can assume that the bitfile is Ok. .

What do I miss with CVI? I ran the same sequence for other bitfile and seemed to be working.

I there any manual/help files for FIFO functions and how to use them? Because I didn't find any. 

Any help is appreciated, thanks in advance. 🙂 

[Dane.S · Accepted solution]

There is some information in the help documents about these functions.

FIFO Method Functions

Acquire FIFO Write Elements

Acquire FIFO Read Elements

Did the example program itself run?

Ensure you are not attempting to access FIFO elements after releasing them. 

[ArtB83]

Hi Dane,

Thanks for your assistance - I've read links that you posted, about READ/WRITE FIFO elements. I followed the example, but didn't run it.

I found a problem in faulty bit arrangement in a data that I pass to FPGA - the firmware was discarding the data upon write, and when I tried to read, there was no data in a FPGA's buffers. So I did some corrections in my software and I was able to receive data and the timeout error disappeared.

In general, as I understand I always have to run the "Release" function, at the END of write/read procedure in order to pass the data from PC host to FPGA_Target, or from FPGA to PC host. But, I can choose either NiFpga_AcquireFifoWriteElements/NiFpga_AcquireFifoReadElements or NiFpga_FifoRead/FifoWrite, to pass the actual data between endpoints (fpga-to-pc pc-to-fpga), depends if I use a local buffer for copying the data into it or receive a buffer pointer, with the data, from Acquire function.