write two CAN ports to one FIFO

[htoton]

Is it possible to write from both CAN0 and CAN1 ports to one FIFO in FPGA VI. I am using a FOR loop to indexing the messages from one port to the FIFO, now wondering if I add the second port how it would work?  both CAN ports try to access the FIFO  would cause problem? is there any other alternatives to use only one memory to write from two ports in FPGA applications?

Thanks for help.

[Christian Mergl]

Hi,

You can write to the FIFO from both channels.

I have two possibilities in mind, first you could create a non-reentrant SubVI which simply has the FIFO Write inside. Since you have a default Timeout of 10 seconds at the CAN Read VIs you should read from the second port in a second loop. From the CAN VIs you get an array of 6 U32 elements where you now need to add another element to determin later if the message is from CAN0 or CAN1.

With that you can write into the FIFO from both Loops independently.

The other way would be to first write all messages from CAN0 into the FIFO and then from CAN1, but keep in mind that the default timout is 10 seconds, which could cause this construct to hang for this time.

Hope this helps,

Christian

[htoton]

Thanks Christian for the reply, I simply used two while loops and write from CAN0 and CAN1 in one fifo, however it is not runing efficiently since the massages have different intervals and there are too many, so to see a specific massage I had to wait quit a bit. Now I turn back to the original solution having seperate fifo for each port.

[Christian Mergl]

Hi,

Did you also think about my first solution, is this not an option for you?

"...first you could create a non-reentrant SubVI which simply has the FIFO Write inside. Since you have a default Timeout of 10 seconds at the CAN Read VIs you should read from the second port in a second loop. From the CAN VIs you get an array of 6 U32 elements where you now need to add another element to determin later if the message is from CAN0 or CAN1."

Thanks,

Christian

[htoton]

Hi,

 I did not  try your first solution, I  think I could not understand it very well. my FPGA vi should have one main loop to read from the first CAN port and the SubVI inside the loop to read from the second port? what would be the sequence of read functions? and how can I write SnbVI to be non-reentrant?

Thanks for help.

[Christian Mergl]

Hi,

I'm sorry if I was not clear enough.

You have to parallel loops, one for CAN0, one for CAN1. From both you get the messages in terms of a 6 element U32 array. In every loop you add a 7th element to this array to determin later if the message is from CAN0 or CAN1. The value of this element is for sure of your choice.

Now you create a SubVI which simply writes this data to an DMA FIFO. Since SubVIs on FPGA are per default reentrant (every SubVI is a new instance), you will need to open the VI Properties, go to the Execution category and change it to non-reentrant.

This SubVI will be placed in both loops now to send the messaged of both CAN bords with a single FIFO.

Hope this helps,

Christian

[htoton]

Thanks Christian for the detail, once I try the method I will let you know the results.

[Kellen]

Hello Christian,

i have now the same situation that shimbloo once had (Time flies)-------"write two CAN ports to one FIFO".

And after read this very Post, i would like try your first solution in practice.

but there is two more question remain since I have not so much experience with LabVIEW / FPGA:

1) Is there anything to do with the default Timeout 10sec of the "CAN Read VIs" that you've mentioned? BTW, I use simply the "FPGA I/O Node" to read the CAN Messages in terms of a 6 element U32 array out and the "FIFO Method / Write" to write them into the DMA FIFO, I have no idea of the "CAN Read VIs" you refer to.

2) Is it a MUST to ues the non-reentrant subVI for the "FIFO Method / Write", while in stead we can set 2 "FIFO Method / Write" in the each of the 2 Loops? Or it does not work properly?

Thanks for reply in advance.

Kellen